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Download Dell 810 System information
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Dell Clock gating (CKE) to conserve power when DIMMs are not accessed Low power self-refresh mode for DIMMs I2C access to SPD EEPROM for access to RDIMM thermal sensors Single-Bit Error Correction SDDC (Single Device Data Correction—x4 or x8 devices) Support for Closed Loop Thermal Management on RDIMMs Multi-Bit Error Detection Support for Memory Mirroring in limited configurations Support for Memory (Rank) Sparing in limited configurations 7.4 Memory Speed Limitations 58B The memory frequency is determined by a variety of inputs: Speed of the DIMMs Speed supported by the CPU (note the DDR3 speed is 1/6 the frequency of the SMI link) BIOS can limit frequency to DDR3 800 based on user power savings configuration in the SETUP menu The R810 supports DDR3 1067 DIMMs. Some CPU SKU’s will have lower SMI link speeds resulting in slower DDR3 buses. Supported frequencies are as follows: SMI link speed at 4.8GT/sec => DDR3 800 SMI link speed of 5.86 GT/sec => DDR3 978 SMI link speed of 6.4 GT/sec => DDR3 1067 NOTE: For Quad-Rank DIMMs mixed with Single- or Dual-Rank DIMMs, the QR DIMM needs to be in the slot with the white ejection tabs (the first DIMM slot in each channel). There is no requirement for the order of SR and DR DIMMs. 7.5 Slots/Risers 59B R810 has all DIMM slots down on the motherboard. There are no memory risers Refer to the Figure 13 for the memory layout. DIMMs A1–A8 correspond to CPU1, DIMMs B1–B8 correspond to CPU2, and so on. In the case where two processors and 2 FlexMem Bridges are installed, DIMMs C1–C8 will associate with CPU1, and DIMMs D1–D8 will associate with CPU2. Dell PowerEdge R810 Technical Guide 29
