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14.3.2 Multiword DMA Settings
IDE multiword DMA setting is done through registers 44h to 47h. The timing for the multiword
DMA modes has two components – the command width, and the recovery width.
Width
Command Width (Cycles)
Recovery Width (Cycles)
MW DMA Mode 2
2h
0h
MW DMA Mode 1
2h
1h
MW DMA Mode 0
7h
7h
The register assignment is as follows:
Register 44h
Primary slave MW DMA timing
Register 45h
Primary master MW DMA timing
Register 46h
Secondary slave MW DMA timing
Register 47h
Secondary master MW DMA timing
Sample Program:
The following Assembly language code sample programs the secondary master to multiword
DMA Mode 2 (i.e., it programs register 47h to 20h).
mov
dx,0CF8h
; To access PCI configuration space, index register
mov
eax,8000A144h
; Device 14h, function 1, registers 44h-47h
out
dx,eax
;
mov
dx,0CFFh
; To access PCI register 47h
mov
al,20h
; Timing for MW DMA Mode 2
out
dx,al
14.3.3 UDMA Mode Settings
IDE UDMA enable/disable is set through register 54h, and the UDMA mode is set through the
registers 56h-57h. The register assignments are as follows:
Register 54h, bit[0]
Primary master.
1 = Enable,
0 = Disable
Register 54h, bit[1]
Primary slave.
1 = Enable,
0 = Disable
Register 54h, bit[2]
Secondary master.
1 = Enable,
0 = Disable
Register 54h, bit[3]
Secondary slave.
1 = Enable,
0 = Disable
Register 56h, bits[2:0]
Primary master UDMA mode, 000b-110b
Register 56h, bits[6:4]
Primary slave UDMA mode, 000b-110b
Register 57h, bits[2:0]
Secondary master UDMA mode, 000b-110b
Register 57h, bits[6:4]
Secondary slave UDMA mode, 000b-110b
© 2008 Advanced Micro Devices Inc.
AMD SB600 BIOS Developer’s Guide (Public Version)
Sample Programs
Proprietary
Page 65