Download Wavecom GX64 Technical data

UART1 is a full featured Universal Asynchronous Receiver Transmitter providing fullduplex asynchronous communication.
UART1 has the following features:
•
32 bytes of FIFO for both receive and transmit
•
FIFO threshold interrupts
•
1 start bit, 7 or 8 data bits, 1 optional parity bit, 1 or 2 stop bits
•
Programmable baud rate
•
Auto-configuration mode with auto-baud and auto-format operation
•
Hardware flow control
•
Software flow control.
Depending upon the user application, some, all, or none of the control signals may be
needed.
Each of the control signals can alternatively be configured as a general
purpose IO. When hardware flow control is not used in communications between the
application and the Wireless CPU®, some applications may require RTS and CTS to be
connected to each other at the Wireless CPU®. Users should familiarize themselves
with the specific implementation of their UART.
The GR64 has a feature in which sleep (lower power) mode can be controlled through
a special handshake protocol using hardware flow control. Details of this protocol
and the AT commands associated with it are contained in a special Application Note,
obtainable through the normal customer support channel.
UART1 converted signals, together with GND, DTM1 and DFM1 form a 9-pin RS232
data port.
The electrical characteristic of this level-shifted signal is described in section 4.3.1.1.
UART1 signals replicate a 9-pin RS232 (V.24) serial port. However, UART1 signal
levels are not compliant with the RS232 (V.28) standard. Conversion between the
Wireless CPU® CMOS levels and RS232 levels can be achieved using a standard
interface IC, such as the Maxim Integrated Products MAX3237. The relationship
between the levels is shown in the following table:
DTM, DFM
RI,RTS,CTS,DSR,DTM,DCD
RS232 level
GR64 level
1
OFF
<-3V
VREF
0
ON
>+3V
0V
GR64 Integrators’ Manual
Page: 62/106
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