Download Motorola M68EVB912B32 Technical data

RST — Module Reset Bit
When set, this bit causes all registers and activity in the module to assume the same state as out of
power-on reset (except for ADPU bit in ATDCTL2, which remains set, allowing the ATD module to remain enabled).
TSTOUT — Multiplex Output of TST[3:0] (Factory Use)
TST[3:0] — Test Bits 3 to 0 (Reserved)
Selects one of 16 reserved factory testing modes.
PORTAD — Port AD Data Input Register
$006F
Bit 7
6
5
4
3
2
1
Bit 0
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
–
–
–
–
–
–
–
–
RESET:
PAD[7:0] — Port AD Data Input Bits
After reset these bits reflect the state of the input pins.
May be used for general-purpose digital input. When the software reads PORTAD, it obtains the digital
levels that appear on the corresponding port AD pins. Pins with signals not meeting VIL or VIH specifications will have an indeterminate value. Writes to this register have no meaning at any time.
ADR0H — ATD Converter Result Register 0
ADR1H — ATD Converter Result Register 1
ADR2H — ATD Converter Result Register 2
ADR3H — ATD Converter Result Register 3
ADR4H — ATD Converter Result Register 4
ADR5H — ATD Converter Result Register 5
ADR6H — ATD Converter Result Register 6
ADR7H — ATD Converter Result Register 7
$007x
RESET:
$0070
$0072
$0074
$0076
$0078
$007A
$007C
$007E
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
–
–
–
–
–
–
–
–
ADRxH[7:0] — ATD Conversion Result
The reset condition for these registers is undefined.
These bits contain the left justified, unsigned result from the ATD conversion. The channel from which
this result was obtained is dependent on the conversion mode selected. These registers are always
read-only in normal mode.
15.3 ATD Mode Operation
STOP — causes all clocks to halt (if the S bit in the CCR is zero). The system is placed in a minimumpower standby mode. This aborts any conversion sequence in progress. During STOP recovery, the
ATD must delay for the STOP recovery time (tSR) before initiating a new ATD conversion sequence.
WAIT — ATD conversion continues unless AWAI bit in ATDCTL2 register is set.
BDM — Debug options available as set in register ATDCTL3.
USER — ATD continues running unless ADPU is cleared.
ADPU — ATD operations are stopped if ADPU = 0, but registers are accessible.
MOTOROLA
114
MC68HC912B32
MC68HC912B32TS/D