Download ADC 10 Specifications

MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
–—– –———–
EXTERNAL
DIGITAL
INPUTS
REFERENCE
(DIN, SCLK,
AT REFADJ
CS , SHDN )
DIN,SCLK, CS Input High Voltage
CONDITIONS
VINH
DIN,SCLK, CS Input Low Voltage
VINL
DIN, SCLK, CS Input Hysteresis
VHYST
DIN, SCLK, CS Input Leakage
TYP
MAX
2.4
VIN = 0V or VDD
DIN, SCLK, CS Input Capacitance
CIN
(Note 5)
SHDN Input High Voltage
VINH
SHDN Input Low Voltage
VINL
SHDN Input Current, High
IINH
SHDN = VDD
SHDN Input Current, Low
IINL
SHDN = 0V
SHDN Input Mid Voltage
VIM
SHDN Voltage, Floating
VFLT
0.8
V
±1
µA
15
pF
V
VDD - 0.5
V
V
4.0
µA
µA
1.5
SHDN = open
0.5
-4.0
SHDN = open
UNITS
V
0.15
IIN
SHDN Max Allowed Leakage,
Mid Input
MIN
VDD - 1.5
2.75
-100
V
V
100
nA
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
VOL
Output Voltage High
VOH
Three-State Leakage Current
Three-State Leakage Capacitance
IL
COUT
ISINK = 5mA
0.4
ISINK = 16mA
ISOURCE = 1mA
0.3
4
V
V
CS = 5V
CS = 5V (Note 5)
±10
µA
15
pF
POWER REQUIREMENTS
Positive Supply Voltage
VDD
Positive Supply Current
IDD
Positive Supply Rejection
(Note 9)
PSR
5 ±5%
V
Operating mode
1.5
2.5
Fast power-down
30
70
Full power-down
2
10
±0.06
±0.5
VDD = 5V ±5%; external reference, 4.096V;
full-scale input
mA
µA
mV
Note 1: Tested at VDD = 5.0V; single-ended, unipolar.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Grounded on-channel; sine wave applied to all off channels.
Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.
4
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