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Timing characteristics
Table 36.
SPEAr600
EXPI - pad signal assignment (continued)
EXPI signal
Direction
PL_GPIOs signal assignment
HLock
Inp.
PL_GPIO_37
HMastlock
Out.
PL_GPIO_38
HBreq
Inp.
PL_GPIO_39
HGrant
Out.
PL_GPIO_40
HResp(1-0)
Bidir.
PL_GPIO(42:41)
HReady_mst
Out.
PL_GPIO_43
HReady_out
Inp.
PL_GPIO_44
HReady_in
Out.
PL_GPIO_45
HSel
Out.
PL_GPIO_46
DMA_LREQ(1:0)/ HAdd(25:24)
Inp.
PL_GPIO(48:47)
DMA_REQ(1:0) / HAdd(27:26)
Inp.
PL_GPIO(50:49)
DMACCLR(1:0)/ HAdd(29:28)
Out.
PL_GPIO(52:51)
DMACTC(1:0) / HAdd(31:30)
Out.
PL_GPIO(54:53)
INT_IN_2
Inp.
PL_GPIO_83
CLK
Bidir.
PL_CLK_1
Reset
Bidir.
PL_CLK_2
INT_IN_1
Inp.
PL_CLK_3
INT_OUT
Out.
PL_CLK_4
Note:
For more details please refer to the Expansion interface (EXPI) chapter of the user manual.
6.2.1
Pad delay disabled
Figure 11. Pad delay disabled block diagram
Q
Q
CLK
D
SET
D
ti n
Q
t o ut
CL R
SET
t ck_ff
CL R
Q
tck _p a d
Note:
66/97
PL_GPIO[ x]
PL _C LK1
The pad of the clock is disabled or enabled using the expi_clk_retim bit in the
EXPI_CLK_CFG register. Refer to the MISC registers chapter of the user manual).
Doc ID 16259 Rev 3