Download External Memory PHY Interface (ALTMEMPHY) (nonAFI

Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
Functional Simulation—the ModelSim Wave and Transcript Window
3–35
This process continues until all 360° (full rate) or 720° (half rate) worth of phases are
sampled and the available data window is measured. The length of time between each
read is determined by the PLL reconfiguration requirements and the compare and
store operation of the sequencer, which is device and configuration dependant. The
gap observed between the first and subsequent reads is greater as the sequencer must
set the PLL into phase stepping mode.
Once a successful range of phases has been sampled, the sequencer center aligns the
PLL phase within this calibrated window. This can be observed on the PLL
reconfiguration bus as a burst of phase changes without any read accesses. In the
example, this calibration is setting on the capture clock phase, so you would (in a
functional simulation) expect a phase of around –90° to be selected. 48 phase steps
were reported during the generation, and a burst of 10 PLL reconfigurations can be
observed (360/48 * 10 = –75°). Refer to Figure 3–10 on page 3–36.
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© January 2010
In Arria GX, Stratix II, and Stratix III devices, calibration is performed on the
resynchronization clock.
Altera Corporation
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide