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BT90.
DMA Restart Hang When First Descriptor is a Legacy Type Following
Channel HALT Due to an Extended Descriptor Error
Problem:
When using multiple DMA channels, all DMA channels may hang if a DMA channel
restart is attempted with a Legacy descriptor as the first descriptor following an error/
HALT on an Extended descriptor on Channel 0 or 1.
Implication:
Following an extended descriptor error on Channel 0 or 1, the channel must be not be
restarted with a first descriptor of legacy type including NULL. Does not apply for single
channel operation.
Workaround: Software must guarantee that the first descriptor processed on restart is an XOR GF
Multiply Generation (base type) before using legacy descriptors with interrupts and
completions.
Status:
For the affected steppings, see the Summary Tables of Changes.
BT91.
JSP CBDMA errata BF508S: Operation With DMA XOR Interrupts/
Completions Enabled Restricted to Channel 0 and 1
Problem:
If DMA XOR interrupts and completions are enabled on channel 0 or 1 concurrent with
operation on channels 2-7, incorrect data transfers can occur on DMA channels 2-7.
DMA XOR interrupts and completions are enabled by setting bits 0 and 3 of descriptor
control field of a DMA XOR with Galios Field Generate/Validate base descriptor.
Implication:
If DMA XOR interrupts and completions are enabled, only one interrupt/completion
type may be used on any single channel and only channels 0 and 1 may be used.
Workaround: Software must either:
• Only use only legacy interrupts and completions on all channels.
• Use only DMA channels 0 and 1 where:
— Only DMA XOR interrupts/completions are enabled on channel 0 and is only
used for DMA XOR operations.
— Only legacy interrupts/completions are enabled on channel 1 and is only used
for DMA legacy operations.
Status:
For the affected steppings, see the Summary Tables of Changes.
BT92.
Suspending/Resetting an Active DMA XOR Channel May Cause an
Incorrect Data Transfer on Other Active Channels
Problem:
Suspending an active DMA XOR channel by setting CHANCMD.Suspend DMA bit (Offset
84; Bit 2) while XOR type DMA channels are active may cause incorrect data transfer
on the other active legacy channels. This erratum may also occur while resetting an
active DMA XOR channel CHANCMD.Reset DMA bit (Offset 84; Bit 5). CHANCMD is in
the region described by CB_BAR(Device 4; function 0-7; Offset 10H) on the processor's
internal IO bus (as defined in the IIOBUSNO register).
Implication:
An incorrect data transfer may occur on the active legacy DMA channels.
Workaround: Software must suspend all legacy DMA channels before suspending an active DMA XOR
channel (channel 0 or 1).
Status:
For the affected steppings, see the Summary Tables of Changes.
BT93.
DWORD-Aligned DMA XOR Descriptors With Fencing and MultiChannel Operation May Cause a Channel Hang
Problem:
DMA XOR descriptors with DWORD aligned sources and fencing enabled may result in a
XOR channel hang until the next platform reset. XOR DMA fencing is set by software in
Descriptor Control.Fence (XOR base descriptor, bit 4)
Implication:
An XOR DMA descriptor with non cacheline aligned sources may hang until the next
platform reset.
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Intel® Xeon® Processor E5 Family
Specification Update, January 2014