1
Download (MC68000)
Transcript
-,
.;..,
.:
::.:
I
,
[
I
., ,..
w,,
I
I
.:
I his input in@ic&{@%
that the data transfers complete. When the processor recognizes
DTACK d~~$~~ia.read
cycle, data is latched “andthe bus cycle is terminated. When
. ...
$~$,&us request, bus grant, and’ bus grant acknowie~ge form a bus arbitration circuit to
$,,;..,
. ‘ch ‘device will bethe ‘bus master.
This input is wire’ORed with all other devices”that could be bus masters. This input
‘indicates to the processor that another device wishes to become the bus master.
:
