Download MCF5475 Reference Manual Errata

Errata for Revision 4
Table 1. MCF5475RM Rev 4 Errata (continued)
Location
Table 10-1/Page 10-2
Description
Replace with the following table:
AD[12:8]1
Clock
Ratio
CLKIN–PCI and
FlexBus Frequency
Range (MHz)
Internal XLB, SDRAM bus,
and PSTCLK Frequency
Range (MHz)
Core Frequency
Range (MHz)
00011
1:2
41.67–66.66
83.33–133.33
166.66–266.66
00101
1:2
25.0–44.42
50.0–88.832
100.0–177.66
01111
1:4
25.0–33.3
100–133.33
200–266.66
NOTES:
1
2
All other values of AD[12:8] are reserved.
Note that DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy down to 75 MHz.
Check with the memory component specifications to verify.
Table 11-1/Page 11-2
Change GSRn’s Access entry to R/W as some status bits may be cleared by writing a 1 to them.
Figure 11-4/Page 11-7
Change GSRn[TEXP, PWMP, COMP, CAPT] bits’ write row to ‘w1c’ as they may be written with
a 1 to clear them.
Table 12-1/Page 12-1
Change SSRn’s Access entry to R/W as some status bits may be cleared by writing a 1 to them.
Figure 12-4/Page 12-4
Change SSRn[BE, ST] bits’ write row to ‘w1c’ as they may be written with a 1 to clear them.
Table 13-1/Page 13-2
Replace table with the one below to better illustrate the interrupt priority and level assignments.
Interrupt
Level
ICR[IL]
Priority
ICR[IP]
Supported Interrupt
Sources
7
6
5
#8–63
4
7
— (Mid-point)
#7 (IRQ7)
3
2
1
#8–63
0
6
5
4
3
2
1
7–4
#8–63
— (Mid-point)
#6 (IRQ6)
3–0
#8–63
7–4
#8–63
— (Mid-point)
#5 (IRQ5)
3–0
#8–63
7–4
#8–63
— (Mid-point)
#4 (IRQ4)
3–0
#8–63
7–4
#8–63
— (Mid-point)
#3 (IRQ3)
3–0
#8–63
7–4
#8–63
— (Mid-point)
#2 (IRQ2)
3–0
#8–63
7–4
#8–63
— (Mid-point)
#1 (IRQ1)
3–0
#8–63
MCF5475 Reference Manual Errata, Rev. 5
Freescale Semiconductor
3