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Delivering Next Generation Technology
Series
Evaluation Board
FPKD-EVB01
Manual
Circuit diagram
TP2
+
C1
100uF
100V C2
33uF
100V
2.2uF
C3
100V
C4
0T-008
2.2uF
0T-008
VOUT+
2
0T-008
JP1
8
VINON_OFF
VOUT-
4
OCPSEL
5
1
1
4
C5
22uF
C6
22uF
25V
25V
+
2
SW1
3
7
SENSE+
100V
3
GND1
CN8
VIN+
1
CN2
0T-008
TP3
DCDC1
CN5
1
+
0T-008
CN4
10uH
C7
22uF
JP2
L1
F1
CCF1F5
not-m
TP1
CN1
C8
220uF
25V
25V
TP4
2
5
2
not-m
6
SDA
11
SDA
TRIM
13
SCL
SMBALERT/PGOOD
14
ADDR1
ISHARE_O
15 ADDR0
SGND
CN9
R3
6
1
VR1
3 500K
0P-008
1
SCL
R1
0T-008
GND1
R2
12
SMBALERT
9
ISHARE
JP3
G3T-12AP
CN3
2
24KΩ
2
10
1
VR2
3 500K
24KΩ
GND2
GND2
CN10
1
2
3
4
5
8
TO ANOTHER DCDC MODULE
B5B-XH-A
15
1
14
CN11
7
13
DCDC1 PIN NUMBER
2
1
SDA
2
SCL
6
3
12
5
TO USB-I2C BOARD
4
SMBALERT
11
B4B-XH-A
10
3
TOP VIEW
4
9
CN12
ISHARE
1
2
3
4
5
TO ANOTHER DCDC MODULE
B5B-XH-A
GND2
Figure 4 Evaluation board circuit diagram
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Page 9
Ver 01.03 Sep 18, 2015