Download DSP56362EVM User Manual

Freescale Semiconductor, Inc.
DSP56362EVMUM/AD
02/01
REV # 2.5
Freescale Semiconductor, Inc...
DSP56362EVM
User’s Manual
Motorola, Incorporated
Semiconductor Products Sector
6501 William Cannon Drive West
Austin, TX 78735-8598
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OnCE is a trademark of Motorola, Inc.
 MOTOROLA INC. 1999, 2000, 2001
Rev. 2.5; published 02/01
Order this document by DSP56362EVMUM/AD
Motorola reserves the right to make changes without further notice to any products herein to improve
reliability, function, or design. Motorola does not assume any liability arising out of the application or use
of any product or circuit described herein; neither does it convey any license under its patent rights nor the
rights of others. Motorola products are not authorized for use as components in life support devices or
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CONTENTS
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Paragraph
Number
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.4
1.4.1
1.4.2
1.4.3
2.1
2.1.1
2.1.1.1
2.1.1.2
2.1.2
2.1.2.1
2.1.2.2
2.1.2.3
2.1.3
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.9.1
2.9.2
2.10
2.10.1
2.10.2
2.10.3
2.11
2.11.1
2.11.2
3.1
5.1
5.2
Title
Page
Number
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3
Evaluation Module Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3
User Supplied Demonstration Hardware . . . . . . . . . . . . . . . . . . . . . .1-3
Required Software Development Hardware . . . . . . . . . . . . . . . . . . . .1-4
Installation Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Hardware Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
PC And Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Analog I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
A/D Converter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
Serial Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
A/D Converter Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Software Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Serial Data Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
D/A Converter Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Analog I/O Blcok Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
S/PDIF Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12
Digital Audio Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13
S/PDIF Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13
Digital I/O Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14
DSP Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15
Host Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15
RS-232/MC68HC711 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16
PLD Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21
Expansion Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23
OnCE Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-24
Direct OnCE Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-24
RS-232/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-25
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-28
EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-28
External Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .2-28
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-29
Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-29
DSP Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-30
Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
Evaluation Module Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
PLD Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
MOTOROLA
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CONTENTS
Paragraph
Number
Page
Number
Pass-Through Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Receive Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Transmit nterrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Main Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Digital Pass-Through. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Digital Pass-Through Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Analog Pass-Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Analog Pass-Through Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
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6.1
6.1.1
6.1.2
6.1.3
6.2
6.3
6.4
6.5
Title
iv
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List of Figures
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Figure
Number
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
MOTOROLA
Title
Page
Number
Figure1-1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Consumer Audio Evaluation and Prototyping Platform . . . . . . . . . . . . . . . .1-2
Demonstration Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
DSP56362EVM Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Default Jumper Locations Shown for Digital Input . . . . . . . . . . . . . . . . . . .2-2
Analog I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Input Clocking Mode Header PLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
JP24, A/D Sampling Rate Select Header . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
D/A Control Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
Analog I/O Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Digital I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
Input Clocking Mode Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12
Primary Digital I/O Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14
Secondary Digital I/O Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14
Host Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15
RS-232 Communication Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16
PLD Clock Outputs - S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17
PLD Clock Outputs - A/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18
DSP Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19
HC08 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20
Operating Mode Jumper (JP8) Location. . . . . . . . . . . . . . . . . . . . . . . . . . .2-22
Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23
RS-232 Communication Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-25
Memory Header Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-27
External Memory Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-28
Evaluation Module Power Supply Diagram . . . . . . . . . . . . . . . . . . . . . . . .2-29
DSP Power Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-30
Receive Input Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
Receive Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
Transmit Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Transmit Interrupt Service Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
Passthrough Main Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5
LCD Pass-through Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6
Jumper Settings for Digital Pass-Through . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
LCD pass-through Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
Jumper Settings for Analog Pass-Through . . . . . . . . . . . . . . . . . . . . . . . . . .6-9
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List of Figures
Title
Page
Number
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Figure
Number
vi
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List of Tables
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Table
Number
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
3-1
5-1
6-1
6-2
MOTOROLA
Title
Page
Number
Jumpers as Installed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
Analog I/O Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
A/D Sampling Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
System, Frame Sync and Serial Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
DAC Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
D/A Software Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
D/A Serial Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Digital I/O Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
S/PDIF Receiver Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12
S/PDIF Transmitter System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13
S/PDIF Transmitter Serial Data Output . . . . . . . . . . . . . . . . . . . . . . . . . .2-13
RS232 Communication with MC68HC711 . . . . . . . . . . . . . . . . . . . . . . .2-16
D/A Converter Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19
DSP Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21
Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23
OnCE Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-24
RS-232 Communications with MC68HC705 . . . . . . . . . . . . . . . . . . . . . .2-25
Memory Line Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26
DSP Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-30
Documentation Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
Evaluation Module Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Digital Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
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List of Tables
Title
Page
Number
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Table
Number
viii
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About This Manual
This manual describes the functionality and use of the DSP56362EVM (Evaluation Module). Motorola offers several different ROM software versions of the DSP56362 that are
supported with this EVM. DSP56362 ROM versions are available to support technologies from third party licenses, such as Dolby Laboratories™, and DTS™.
Users can upgrade this EVM because critical components such as the DSP56362,
MC68HC711, and EPROM are socketed. For information on other ROM versions, contact Motorola, or visit the website at:
Freescale Semiconductor, Inc...
http://mot-sps.com/ADC/audio_solutions.html
Organization
This book is organized into 6 sections:
•
•
•
•
•
•
Overview
Setup and Operation
Component Datasheets
Schematics
Bill of Materials
Running the Pass-through code
Suggested Reading
Additional reading that provides background for the information in this guide as well as
general information about the Multimedia Architecture:
•
•
IEC 958 Digital Audio Interface Standard
DSP56362 User’s Manual
Conventions
This document uses the following notational conventions:
•
•
•
Messages displayed on screen and example code are presented in the courier
fixed-width font.
Information entered by users is shown in bold font.
File names, program names, and directories are in italics.
MOTOROLA
About This Manual
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OVERVIEW
Introduction
SECTION
1
OVERVIEW
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1.1
INTRODUCTION
This section describes the basic features, hardware description and installation of the
DSP56362EVM (Evaluation Module). The manual also describes the equipment and software
required. Code samples and self-test code are provided on an accompanying software diskette.
The schematic diagram and parts of the Evaluation Module are included in this manual. This
is a generic hardware/software configuration. Upgrade kits are available for more specialized
and advanced applications. Some upgrade kits require licensing agreements with other
companies (DTS™, Dolby Digital™, etc.).The block diagram is shown in Figure1-1.
External Memory
User Interface
DSP56362
LCD Display
MC68HC711
SRAM
128K x 24
SHI
Buttons/
Keypad
SDI0
A/D
PCM1800
Analog Input
SDI1
S/PDIF
Receiver
Digital Input
S/PDIF
Transmitter
RS-232
DEBUG
Computer
Optional Output
For Testing
SDI0
D/A
PCM1716
L/R Main
SDI1
D/A
PCM1716
Center/Sub
SDI2
D/A
PCM1716
L/R Surround
SDI3
D/A
PCM1716
JTAG
68 HC705C8A
EPROM
128K x 8
Headphone Mixdown
or Aux Surround
Figure 1-1 Figure1-1 Block diagram
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DSP56362EVM User’s Manual
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1-1
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OVERVIEW
Feature Description
1.2
FEATURE DESCRIPTION
Freescale Semiconductor, Inc...
The DSP56362EVM is a low-cost platform for multichannel digital audio applications design,
prototyping, and development. See Figure1-2.
Figure 1-2 Consumer Audio Evaluation and Prototyping Platform
The fully assembled and tested circuit board contains the following.
•
24-bit DSP56362 Digital Signal Processor operating at 80-100MHz.
•
128k x 24-bits of external SRAM and 128k x 8-bits of EPROM.
•
One 20-bit stereo Analog-to-Digital converter (ADC), four 24-bit stereo
Digital-to-Analog converters (DACs).
•
RCA jacks for all analog audio input and output connections.
1-2
DSP56362EVM User’s Manual
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OVERVIEW
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Hardware Description
•
Optical and transformer-isolated electrical S/PDIF stereo digital audio inputs and
outputs.
•
50-pin expansion connector that provides capability for expansion and/or substitution
of other input/output peripherals. This connector also simplifies interprocessor
communication between other Motorola Evaluation Modules.
•
Socketed MC68HC711E20 that allows users to substitute custom MC68HC711 code
(allows connection to MC68HC11 emulation systems).
•
2 line x 20 character Liquid Crystal Display (LCD) and four soft switches for user
interface.
•
MC68HC705C8 microcontroller that performs RS-232-to-OnCE port command
conversions.
1.3
HARDWARE DESCRIPTION
This section gives a brief summary of the Evaluation Module hardware supplied, and
description of the hardware required to use the Evaluation Module.
1.3.1
EVALUATION MODULE HARDWARE
•
Evaluation Module board
•
Domain Technologies CD
•
Debug - Evaluation Module manual is provided on the CD-DSP56362EVM User’s
Manual (this document)
1.3.2
USER SUPPLIED DEMONSTRATION HARDWARE
•
An AC-3 or PCM bitstream source such as a Laserdisc, DAT, CD source, or VHS.
•
An audio amplifier that can drive headphones or speakers as shown in Figure1-3.
•
A 7.5- 9V 1 amp AC/DC power supply (7.5 volts is preferred).
MOTOROLA
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OVERVIEW
Hardware Description
L
R
Ls
Rs
C
Sub
La
Ra
Lin
Rin
Subwoofer
(powered)
Power Amp
Subwoofer
(unpowered)
Elec.
out
Opt.
in
Elec.
in
JP12
BB1716
JP8
JP16
JP15
JP7 JP5
68HC11E9
BB1716
BB1716
BB1716
12032
ISPLS
DSP56362
JP20
DIR1700
P1
CS8414
JP20
JP2
JP31
JP21 JP23 JP25
Laserdisc/DVD Player
IR Rx
GS71108J-10
GS71108J-10
GS71108J-10
JP14
JP13
JP22
JP19
JP10
JP24
P2
JP4
P3
JP11
BB1800
JP18
CS8404
Freescale Semiconductor, Inc...
Elec.
out
Listener
DSP56362EVM
Figure 1-3 Demonstration Configuration
1.3.3
REQUIRED SOFTWARE DEVELOPMENT HARDWARE
•
A personal computer with x386 or higher processor, minimum 2 Mbytes of memory,
CD ROM driver, and a serial port that is capable of at least 19,200 bits-per-second
data transfer rate.
•
Windows 95/98 or NT operating system
•
An RS-232 cable (DB9 male to DB9 female)
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OVERVIEW
Installation Procedures
1.4
INSTALLATION PROCEDURES
Installing the Evaluation Module requires four steps:
1. Preparing the board.
2. Connecting the board to the PC and power.
3. Installing the software on the PC.
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4. Testing the installation.
1.4.1
HARDWARE CONNECTIONS
CAUTION
Because all electronic components are sensitive to the effects of electrostatic
discharge (ESD) damage, use correct procedures when handling all components in
this kit and inside the supporting PC. Use the following procedures to minimize the
possibility of ESD damage.
•
Always handle all static-sensitive components in a protected area, preferably a
lab with conductive (anti-static) flooring and bench surfaces.
•
Always use grounded wrist straps when handling sensitive components.
•
Never remove components from anti-static packaging until required for
installation.
•
Always transport sensitive components in anti-static packaging.
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OVERVIEW
Installation Procedures
1.4.2
PC AND POWER CONNECTIONS
Figure1-4 shows the interconnection diagram for connecting the PC and the external power
supply to the Evaluation Module board.
DB9 Interface
Cable
External
7-9V
Power
Freescale Semiconductor, Inc...
PC-compatible
Computer
P1
Connect cable
to RS-232 port
P2
or
P3
DSP56362EVM
Figure 1-4 DSP56362EVM Cable Connections
1. Connect the DB9P interface cable to the RS-232 port connection on the PC, and P1 on
the Evaluation Module board. This provides the connection to allow the PC to control
the board function.
2. Apply 7.5-9V AC/DC 1amp power to the P2 or P3 connector on the Evaluation
Module board.
3. The green Power LED will light when power is correctly applied.
1.4.3
SOFTWARE INSTALLATION
The Evaluation Module demonstration software consists of a Domain Technologies CD
containing Windows™ style user interface debug software and demonstration/test code.Use
the following steps to install the software:
1. Insert the Domain Technologies CD into the CD-ROM drive. Select and run the
program setup.exe. Choose DSP563xxEVM from the menu.
2. Choose Debug 56k from the menu.
3. A Software License Agreement will appear. To install EVM563xx, you must accept
this agreement. Click yes.
4. A new screen will appear. Fill in your name and company, then choose NEXT.
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OVERVIEW
Installation Procedures
5. Setup will install EVM563xx in C:\Program Files\DomTech\EVM563xx, then
choose NEXT.
6. Setup will add program icons to the Program Folder. You may type a new folder
name, or select one from the existing Folders list. Click NEXT to continue.
7. Setup has enough information to start copying the program files. Click NEXT to begin
copying files.
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8. The screen will clear and the Domain menu will appear. Click EXIT.
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OVERVIEW
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Installation Procedures
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SETUP AND OPERATION
SECTION
2
Freescale Semiconductor, Inc...
SETUP AND OPERATION
This section describes the setup options that you need to be familiar with. Jumpers on the
Evaluation Module are provided to configure the board for various operations. The factory
default jumpers are shown in Table 2-1. The locations of the headers for jumpers is shown in
Figure 2-1.l
Table 2-1 Jumpers as Installed
Jumper
From
To
JP1
1
JP2
Jumper
From
To
Jumper
From
To
2
3
4
JP20
1
2
1
2
5
6
JP21
1
2
JP3
1
2
7
8
JP23
1
2
JP4
1
2
9
10
JP24
1
2
JP5
1
2
11
12
JP25
1
2
JP6
1
2
13
14
JP27
1
2
JP7
1
2
17
18
1
3
JP28
3
4
JP8
7
MOTOROLA
8
JP12
19
20
2
4
21
22
2
3
23
24
5
6
25
26
8
9
29
30
11
12
31
32
14
15
33
34
35
36
43
44
45
46
47
48
JP31
S6
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2-1
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SETUP AND OPERATION
Figure 2-1 Default Jumper Locations Shown for Digital Input
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SETUP AND OPERATION
Analog I/O Description
2.1
ANALOG I/O DESCRIPTION
The Evaluation Module has two analog input channels (Left and Right) and eight analog
output channels.
1. Left
2. Right
3. Center
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4. Subwoofer
5. Left Surround
6. Right Surround
7. Auxiliary channel 1
8. Auxiliary channel 2
Figure2-2 shows the analog input and output connectors.
J8
J7
R
RS
S
Raux
Rin
L
LS
C
Laux
Lin
Figure 2-2 Analog I/O Connectors
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SETUP AND OPERATION
Analog I/O Description
The A/D and D/A converters are clocked by the oscillators. Configure the header for analog
input using the parameters as shown in the following table.
Table 2-2 Analog I/O Clocking Mode
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JP 20
Pins 1-2
MODE
ON
CLOCKED BY S/PDIF RECEIVER
(DIGITAL INPUT)
OFF
CLOCKED BY OSCILLATOR
(ANALOG INPUT)
U11
PLD
JP20
37
72
JP4
73
36
144
108
109
DSP
U2
1
Figure 2-3 Input Clocking Mode Header PLD
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SETUP AND OPERATION
Analog I/O Description
2.1.1
A/D CONVERTER DESCRIPTION
The system clock 256FS_CLK is input to the A/D and varies according to the selected
oscillator which should be chosen according to the desired input sampling rate. Select the
desired sampling rate by placing a jumper on the following header.
Table 2-3 A/D Sampling Rate Select
JP24
Pins 1-2
Pins 3-4
32 KHZ
On
On
44.1 KHZ
On
Off
48 KHZ
Off
On
96 KHZ
Off
Off
Note:
If U26 is populated with part number
CS8412, the maximum sampling rate
will be 48 KHZ.
72
3
37
73
1
36
JP4
JP24
108
109
DSP
U2
144
Freescale Semiconductor, Inc...
Sampling
Frequency
1
Figure 2-4 JP24, A/D Sampling Rate Select Header
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SETUP AND OPERATION
Analog I/O Description
The receive and transmit serial clocks SCKR/SCKT operate synchronously and are derived
from the PLD as BIT_CLK. The receive and transmit frame syncs FSR/FST also operate
synchronously and are derived from the PLD as FS_CLK. These signals are derived from the
PLD which divides the 256FS_CLK by 256 and by 4 to generate FS_CLK and BIT_CLK,
respectively. The table below shows the clock relationships.
Freescale Semiconductor, Inc...
Table 2-4 System, Frame Sync and Serial Clocks
256FS_CLK
FS_CLK
BIT_CLK
8.192 MHZ
32 KHZ
2.048 MHZ
11.2896 MHZ
44.1 KHZ
2.8224 MHZ
12.288 MHZ
48 KHZ
3.072 MHZ
24.576 MHZ
96 KHZ
6.144 MHZ
2.1.1.1
Serial Data Input
The A/D converter sends audio data to the DSP on the serial data input SDI0.
2.1.1.2
A/D Converter Reset
The A/D converter is reset by asserting the RESET signal of the DSP.
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SETUP AND OPERATION
Analog I/O Description
2.1.2
D/A CONVERTERS
The system clock 256FS_CLK is input to the D/As and varies according to the selected
oscillator that corresponds to the input’s sampling rate as described in Table 2-3. The four
D/A converters operate in the slave mode so that the serial clock BIT_CLK and frame sync
FS_CLK are inputs to the D/A converters.
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2.1.2.1
Software Mode
The D/A converters operate in the software mode allowing for user control of the following
functions:
•
Input audio data format
•
De-emphasis control
•
Soft mute control
•
Attenuation control
•
Output phase selection
•
DAC operation control
The default D/A converter settings are shown in the following table.
Table 2-5 DAC Default Settings
MOTOROLA
DESCRIPTION
DEFAULT
Audio data format
24-bit I2S
Left channel attenuation
0 dB
Right channel attenuation
0 dB
Soft mute
OFF
De-emphasis
OFF
DAC operation
ON
Zero detect mute
OFF
Output analog signal phase
Normal
Attenuation control
Individual channel
L/R polarity
Left low/Right high
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SETUP AND OPERATION
Analog I/O Description
The MC68HC711 microcontroller performs D/A converter initialization. DSP control of the
D/A converters requires custom software. Refer to the Burr-Brown PCM1716E datasheet for
detailed information on initializing the D/A converters. Table 2-6 describes the software mode
control settings.
Table 2-6 D/A Software Mode Control
SELECT
CONTROL BY
DSP
CONTROL BY
PLD
1-2
2-3
DA0 - L/R
4-5
5-6
DA1 - LS/RS
7-8
8-9
DA2 - C/S
10-11
11-12
DA3 - AUX L/R
13-14
14-15
ML
37
72
Freescale Semiconductor, Inc...
JP31
73
36
144
108
109
DSP
U2
1
1
4
7
10
13
3
6
9
12
15
JP31
Figure 2-5 D/A Control Header
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SETUP AND OPERATION
Analog I/O Description
2.1.2.2
Serial Data Outputs
The D/A converters receive audio data from the DSP on the following serial data outputs:
Freescale Semiconductor, Inc...
Table 2-7 D/A Serial Data Outputs
D/A
SDOx
L/R
SDO0
LS/RS
SDO1
C/S
SDO2
AUX L/R
SDO3
2.1.2.3
D/A Converter Reset
Asserting the DSP RESET signal, resets the D/A converters.
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SETUP AND OPERATION
Analog I/O Description
2.1.3
ANALOG I/O BLOCK DIAGRAM
The following figure shows the functional block diagram of the analog I/O circuitry:
FS_CLK
BIT_CLK
Freescale Semiconductor, Inc...
DAC0
DAC1
DAC2
DSP56362
ADC
SDI0
SDO0
SDO1
SDO2
SDO3
DAC3
256FS_CLK
Figure 2-6 Analog I/O Block Diagram
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SETUP AND OPERATION
Digital I/O
2.2
DIGITAL I/O
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The Evaluation Module has coaxial and optical inputs, two coaxial and optical outputs, and it
supports digital coaxial I/Os, and optical I/Os. The primary set of digital outputs are
connected to the DSP Digital Audio Transmitter (DAX). The secondary set of digital outputs
are connected to the S/PDIF transmitter. Figure 2-7 shows the digital input and output
connector configuration.
J6
OPTICAL
J2
OPTICAL
J5
COAX
J4
OPTICAL
J3
COAX
J1
COAX
S/PDIF OUTPUT
SECONDARY - S/PDIF TX
S/PDIF OUTPUT
PRIMARY - DSP DAX PORT
S/PDIF INPUT
Figure 2-7 Digital I/O Connectors
Configure the JP20 header for digital input. Refer to Figure 2-1 and Figure 2-7.
Table 2-8 Digital I/O Clocking Mode
JP20
PINS 1-2
MOTOROLA
MODE
ON
CLOCKED BY S/PDIF RECEIVER
(DIGITAL INPUT)
OFF
CLOCKED BY OSCILLATOR
(ANALOG INPUT)
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SETUP AND OPERATION
Digital I/O
U11
PLD
JP20
73
36
108
144
DSP
U2
109
Freescale Semiconductor, Inc...
37
72
JP4
1
Figure 2-8 Input Clocking Mode Header
2.2.1
S/PDIF RECEIVER
The S/PDIF receiver recovers audio data and low jitter clocks from a digital audio
transmission line. The generated clocks are the serial clock (BIT_CLK), frame sync
(FS_CLK), and system clock (256FS_CLK). The S/PDIF receiver takes either coaxial or
optical input. Selection is made by the position of S6 as follows:
Table 2-9 S/PDIF Receiver Select
S/PDIF INPUT
S6
Switch Position
COAXIAL
1
ELC
OPTICAL
2
OPT
The S/PDIF receiver sends audio data to the DSP on the serial data input SDI1.
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SETUP AND OPERATION
Digital I/O
2.2.2
DIGITAL AUDIO TRANSMITTER
The Digital Audio Transmitter (DAX) outputs digital audio data in the AES/EBU, CP-340,
and IEC958 formats. The DAX port connects to both coaxial and optical output connectors
while the DAX clock input line (ACI) can be connected to an external clock source. This
clock source must be 256fs, 384fs, or 512fs. The DSP transmits audio and non-audio data on
the ADO pin.
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2.2.3
S/PDIF TRANSMITTER
The S/PDIF transmitter operates in the consumer mode. The master clock 128FS_CLK varies
according to the input sampling rate:
Table 2-10 S/PDIF Transmitter System Clock
SAMPLING
FREQUENCY
128FS_CLK
FS_CLK
BIT_CLK
32KHZ
4.096MHZ
32KHZ
2.048MHZ
44.1KHZ
5.6448MHZ
44.1KHZ
2.8224MHZ
48KHZ
6.144MHZ
48KHZ
3.072MHZ
I2S is the audio data format utilized on the DSP56362EVM.
The S/PDIF transmitter receives data from the DSP on the serial data output SDOx line. The
SDOx is configured by placing a jumper on the JP27 header as shown below:
Table 2-11 S/PDIF Transmitter Serial Data Output
MOTOROLA
SDOx
JP27
SDO0
1-2
SDO1
3-4
SDO2
5-6
SDO3
7-8
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SETUP AND OPERATION
Digital I/O
2.2.4
DIGITAL I/O BLOCK DIAGRAM
The functional block diagrams of the primary and secondary digital I/O circuits are shown in
Figure 2-9 and Figure 2-10, respectively.
DSP
EXTERNAL CLOCK SOURCE
ACI
ADO
J1 or J2
Figure 2-9 Primary Digital I/O Block Diagram
J3 OR J4
SDI1
SDOx
DSP
J5 OR J6
S/PDIF TX
BIT_CLK
FS_CLK
S/PDIF RX
256FS_CLK
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256FS, 384FS, OR 512FS
PLD
BIT_CLK
FS_CLK
128FS_CLK
Figure 2-10 Secondary Digital I/O Block Diagram
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SETUP AND OPERATION
DSP Clock
2.3
DSP CLOCK
The DSP clock is derived from the 8.192Mhz oscillator Y4. A voltage level converter is used
because the DSP’s EXTAL requires 3.3V operation. The PINIT signal is tied low, which
disables the PLL when it resets. Because of this, the PLL’s multiplication factor must be
configured in user software. If the multiplication factor is not set, the DSP operating clock is
4.096Mhz (half of 8.192Mhz). Refer to Figure 2-15 for more information.
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2.4
HOST MICROCONTROLLER INTERFACE
The MC68HC711E20 microcontroller communicates with the DSP using the Serial Host
Interface (SHI) port in SPI mode. When SS is pulled low by the microcontroller, the
microcontroller can write to the DSP. The MOSI and MISO lines pass control data through
the DSP SHI in 24-bit mode. SCK is the SPI Shift Clock from the DSP.
The microcontroller also receives commands from the momentary push-button switches S2,
S3, S4, or S5. The results of these commands are then displayed by a modular LCD panel with
a 2 x 20 line character display. These commands control the settings of the executed software.
The microcontroller also receives status information from the DSP.
MC68HC711
LCD
DSP
MOSI
MISO
SCK
Figure 2-11 Host Microcontroller Block Diagram
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SETUP AND OPERATION
RS-232/MC68HC711 Interface
2.5
RS-232/MC68HC711 INTERFACE
Configure the header as shown in the following table, when using the RS-232 transceiver to
communicate with the MC68HC711 microcontroller.
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Table 2-12 RS232 Communication with MC68HC711
PINS
JP28
3-5
JUMPER
4-6
JUMPER
1
3
5
2
4
6
JP28
D8
Y5
Figure 2-12 RS-232 Communication Select
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SETUP AND OPERATION
PLD Functions
2.6
PLD FUNCTIONS
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The PLD performs the following functions:
•
Determines if S/PDIF or analog input is present.
•
Performs clock division.
•
Generates the DSP clock.
•
Selects DACs for initialization.
•
Inverts RESET signal for the HC08 microcontroller.
The PLD determines if the input to the DSP comes from the S/PDIF receiver or the A/D
converter. If JP20 is jumpered (JUMP = logic 0) the PLD is notified that the input is from the
S/PDIF receiver. In this case, the system clock, left/right clock, and bit clock that are
generated by the S/PDIF receiver, are passed through the PLD as shown in Figure 2-13.
PLD
CS_SCK
256FS_CLK
CS_LRCK
FS_CLK
CS_MCK
BIT_CLK
Figure 2-13 PLD Clock Outputs - S/PDIF
If JP20 is not jumpered (JUMP = logic 1) then the PLD assumes that the input is from the A/D
converter. In this case, the system clock, left/right clock, and bit clock are generated from
oscillators depending on the selected sampling rate on JP24. Figure 2-14 shows these
sampling rates.
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SETUP AND OPERATION
PLD Functions
32Khz Sampling Rate
PLD
8.192Mhz
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44.1Khz Sampling Rate
256FS_CLK
( 8.192Mhz ) ³ ( 256 )
FS_CLK
( 8.192Mhz ) ³ ( 4 )
BIT_CLK
PLD
11.288Mhz
48Khz Sampling Rate
24.576Mhz
96Khz Sampling Rate
256FS_CLK
( 11.288Mhz ) ³ ( 256 )
FS_CLK
( 11.288Mhz ) ³ ( 4 )
BIT_CLK
PLD
( 24.576Mhz ) ³ ( 2 )
256FS_CLK
( 24.576Mhz ) ³ ( 512 )
FS_CLK
( 24.576Mhz ) ³ ( 8 )
BIT_CLK
PLD
24.576Mhz
256FS_CLK
( 24.576Mhz ) ³ ( 256 )
FS_CLK
( 24.576Mhz ) ³ ( 4 )
BIT_CLK
Figure 2-14 PLD Clock Outputs - A/D
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SETUP AND OPERATION
PLD Functions
The default DSP clock source is 8.192 Mhz. If another clock source is required, modify the
PLD equations and reprogram the PLD.
PLD
DSP_CLK
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8.192Mhz
Figure 2-15 DSP Clock Source
All D/A converters are initialized after reset. For example, DA_SEL2 = logic 1, DA_SEL1 =
logic 0, DA_SEL0 = logic 0. To individually initialize the D/A converters, modify the
MC68HC711 microcontroller code to reflect the necessary changes.
Table 2-13 D/A Converter Select
MOTOROLA
D/A
INITIALIZED
DA_SELx = 1
DA_SELx = 0
DA0
DA_SEL0
DA_SEL1
DA_SEL2
DA1
DA_SEL1
DA_SEL0
DA_SEL2
DA2
DA_SEL1
DA_SEL2
DA_SEL0
ALL DAs
DA_SEL2
DA_SEL0
DA_SEL1
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SETUP AND OPERATION
PLD Functions
The PLD inverts the output from the RS-232 transceiver to the HC08 microcontroller as
shown in the following figure.
PLD
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RESET_MCU
RESET_MCU
Figure 2-16 HC08 Reset
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SETUP AND OPERATION
Operating Mode Selection
2.7
OPERATING MODE SELECTION
DSP operating modes are selected by configuring JP8 as shown in Figure 2-17 and in the
following table.
Table 2-14 DSP Operating Mode
JP8
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MODE
DESCRIPTION
PINS 7-8
MODD
PINS 5-6
MODC
PINS 4-3
MODB
PINS 2-1
MODA
0
EXPANDED MODE
ON
ON
ON
ON
1
BOOTSTRAP FROM BYTE-WIDE MEMORY
ON
ON
ON
OFF
2
JUMP TO PROM STARTING ADDRESS
ON
ON
OFF
ON
5
BOOTSTRAP FROM SHI (SLAVE SPI MODE)
ON
OFF
ON
OFF
7
BOOTSTRAP FROM SHI (SLAVE I2C MODE)
ON
OFF
OFF
OFF
8
EXPANDED MODE
OFF
ON
ON
ON
C
HI08 BOOTSTRAP IN ISA MODE
OFF
OFF
ON
ON
D
HI08 BOOTSTRAP IN MC68HC711 NON-MUX MODE
OFF
OFF
ON
OFF
E
HI08 BOOTSTRAP IN 8051 MUX BUS MODE
OFF
OFF
OFF
ON
F
HI08 BOOTSTRAP IN 68302 BUS MODE
OFF
OFF
OFF
OFF
Refer to the DSP56362 User’s Manual for a detailed description of the operating modes.
MOTOROLA
DSP56362EVM User’s Manual
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Freescale Semiconductor, Inc.
SETUP AND OPERATION
Operating Mode Selection
U7
Y1
Freescale Semiconductor, Inc...
JP8
Figure 2-17 Operating Mode Jumper (JP8) Location
2-22
DSP56362EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
SETUP AND OPERATION
Expansion Port
2.8
EXPANSION PORT
The expansion port connector allows users to connect the DSPÆs SHI, ESAI, DAX and
Timer ports to other input and output devices.
Table 2-15 Expansion Connector
JP12
JP12
EXTERNALSIDE
DSP SIDE
1
2
3
SIGNAL
EXTERNALSIDE
DSP SIDE
+3.3V
27
28
GND
4
MOSI
29
30
FST
5
6
MISO
31
32
FSR
7
8
SCK
33
34
SCKT
9
10
SS
35
36
SCKR
11
12
HREQ
37
38
HCKT
13
14
+5V
39
40
HCKR
15
16
SDO0
41
42
GND
17
18
SDO1
43
44
ADO
19
20
SDO2
45
46
ACI
21
22
SDO3
47
48
TIO0
23
24
SDI1
49
50
GND
25
26
SDI0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Freescale Semiconductor, Inc...
SIGNAL
JP12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Figure 2-18 Expansion Connector
MOTOROLA
DSP56362EVM User’s Manual
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2-23
Freescale Semiconductor, Inc.
SETUP AND OPERATION
OnCE Port
2.9
ONCE PORT
The Evaluation Module has an on-chip emulation (OnCE™) connector that provides a means
of interacting with the DSP and its peripherals non-intrusively. This allows users to examine
registers, memory, or on-chip peripherals which facilitates hardware and/or software
development. Perform debugging with the OnCE™ port in two ways.
1. A direct OnCE™ connection for use with an external command converter.
Freescale Semiconductor, Inc...
2. A serial RS-232/OnCE™ connection for use with the on-board command converter.
2.9.1
DIRECT ONCE CONNECTION
The OnCE connector allows an external command converter to communicate with the DSP.
The following table specifies the OnCE signals. Refer to Figure 2-1 for location of JP10.
Table 2-16 OnCE Port Connector
2-24
JP10
PIN
SIGNAL
JP10
PIN
SIGNAL
1
TDI
2
GND
3
TDO
4
GND
5
TCK
6
GND
7
NO CONNECT
8
NO CONNECT
9
RESET
10
TMS
11
+3.3V
12
NO CONNECT
13
DE
14
TRST
DSP56362EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
SETUP AND OPERATION
OnCE Port
2.9.2
RS-232/ONCE INTERFACE
Freescale Semiconductor, Inc...
The on-board command converter also allows debugging using the OnCE port. The
RS-232/OnCE interface receives the serial data from the RS-232 transceiver and executes
commands sent by the host computer. These commands can reset the DSP, put the DSP in
debug mode, release the DSP from debug mode, read and write to the OnCE port, and read
and write to the DSP itself. The RS-232 serial communication is performed in software on the
MC68HC705 microcontroller. When using the RS-232 transceiver to communicate with the
MC68HC705C8, configure the header as shown in the following table. Refer to Figure 2-1
and Figure 2-19 for header location.
Table 2-17 RS-232 Communications with MC68HC705
PINS
JP28
1-3
JUMPER
2-4
JUMPER
1
3
5
2
4
6
JP28
Figure 2-19 RS-232 Communication Select
MOTOROLA
DSP56362EVM User’s Manual
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2-25
Freescale Semiconductor, Inc.
SETUP AND OPERATION
Memory
2.10
MEMORY
The Evaluation Module has glueless connection to external SRAM and EPROM. The
following memory lines are connected to an expansion header. See Figure 2-20.
Table 2-18 Memory Line Settings
PIN
SIGNAL
HEADER
PIN
SIGNAL
HEADER
PIN
SIGNAL
JP13
1
D0
JP14
1
A0
JP15
3
AA0
2
D1
2
A1
5
AA1
3
D2
3
A2
7
AA2
4
D3
4
A3
9
AA3
7
D4
5
A4
4
BB
8
D5
6
A5
6
BG
9
D6
7
A6
8
BR
10
D7
8
A7
10
TA
13
D8
9
A8
11
RD
14
D9
10
A9
12
CAS
15
D10
11
A10
13
WR
16
D11
12
A11
19
D12
13
A12
20
D13
14
A13
21
D14
15
A14
22
D15
16
A15
25
D16
17
A16
26
D17
18
A17
27
D18
28
D19
31
D20
32
D21
33
D22
34
D23
Freescale Semiconductor, Inc...
HEADER
2-26
DSP56362EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
SETUP AND OPERATION
Freescale Semiconductor, Inc...
Memory
Figure 2-20 Memory Header Locations
MOTOROLA
DSP56362EVM User’s Manual
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2-27
Freescale Semiconductor, Inc.
SETUP AND OPERATION
Memory
2.10.1
SRAM
The Evaluation Module has 128k x 24-bits of external asynchronous static RAM (SRAM). To
keep the address stable during the entire bus cycle, insert a minimum of 1 wait state to the bus
operation.
Freescale Semiconductor, Inc...
Select the SRAM by configuring the DSP’s address attribute register to assert the AA2 line.
The SRAM can be upgraded up to 512k x 24-bits. When using 512k x 24-bits of SRAM, the
upper half of memory is accessible by controlling the address attribute line AA0. AA0 is
connected to the memory’s most significant address line.
2.10.2
EPROM
The Evaluation Module has 128k x 8-bits of EPROM. To keep the address stable during the
entire bus cycle, insert a minimum of 1 wait state to the bus operation.
Select the EPROM by configuring the DSP’s address attribute register to assert the AA1 line.
2.10.3
EXTERNAL MEMORY BLOCK DIAGRAM
The following figure shows the functional block diagram of the external memory
interface.Memory data is accessible through the JP13-JP15 headers.
ADDRESS
A0..A17
JP14
DSP
SRAM
A0..A17
EPROM
A0..A16
A18
CE
AA0
AA2
AA1
CE
JP15
D0..D7
D0..D23
DATA
D0..D23
JP13
Figure 2-21 External Memory Interface Diagram
2-28
DSP56362EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
SETUP AND OPERATION
Power Supply
2.11
POWER SUPPLY
The Evaluation Module requires an input voltage of 7.5-9V AC/DC (recommended 1A) for
both analog and digital circuits. It has separate digital and analog power and ground planes
and voltage regulators to output the +5V, +5VA and +3.3V supplies. The DC-DC converter
outputs the -5V supply. When power is supplied to the 2.1mm power connector P2 or to the
2-pin terminal block P3, the green LED D8 is powered on. The polarity of the voltage applied
to the P3 terminal block is reversible because the power goes through a bridge rectifier.
Freescale Semiconductor, Inc...
Note:
While the voltage regulators can accommodate higher input voltage potentials, the
added heat dissipation required at these input voltage levels results in the regulator
becoming dangerously warm. It is recommended that users do not subject the
board to power inputs in excess of the 12V.
2.11.1
POWER SUPPLY BLOCK DIAGRAM
The following figure shows the functional block diagram of the power supply circuit.
+5V
+5VA
5V REGULATOR
P2 OR P3
7.5 — 9V AC/DC
DC-DC CONVERTER
3.3V REGULATOR
- 5V
3.3V
Figure 2-22 Evaluation Module Power Supply Diagram
MOTOROLA
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Freescale Semiconductor, Inc.
SETUP AND OPERATION
Power Supply
2.11.2
DSP POWER
For power consumption measurement, jumpers are available to connect the DSP’s power pins
to the power supply. Jumpers are placed in the headers shown in Table 2-19, the Evaluation
Module supplies power to the DSP. Jumpers can be removed to provide access for power
measurements.
Freescale Semiconductor, Inc...
Table 2-19 DSP Power Supply
JPx
POWER
DESCRIPTION
JP1
VCCC
BUS CONTROL
JP2
VCCD
DATA BUS
JP3
VCCH
HOST
JP4
VCCA
ADDRESS BUS
JP5
VCCS
SHI, ESAI, DAX, TIMER
JP6
VCCQL
QUIET CORE (LOW) POWER
JP7
VCCQH
QUIET CORE (HIGH) POWER
JP1 JP5 JP3
37
72
36
73
JP4
JP8
144
108
109
JP2
JP7
DSP
U2
1
Figure 2-23 DSP Power Jumpers
2-30
DSP56362EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
COMPONENT DATASHEETS
Documentation
SECTION
3
COMPONENT DATASHEETS
Freescale Semiconductor, Inc...
3.1
DOCUMENTATION
Documentation for the audio components can be downloaded from the manufacturer websites
shown in the following table. The Motorola web site for the appropriate manuals is:
http://www.mot.com/pub/SPS/DSP/LIBRARY/
Table 3-1 Documentation Location
Motorola
Devices
DESCRIPTION
DSP56362
Product Brief
DSP56362P/D
Technical Datasheet
DSP56362/D
Motorola Document Order Number
User Manual
DSP56362UM/D
Family Manual
DSP56300FM/D
Other
Devices
DESCRIPTION
PCM1800
Technical Datasheet
http://www.burr-brown.com/download/DataSheets/PCM1800.pdf
PCM1716
Technical Datasheet
http://www.burr-brown.com/Products/DataSheets/PCM1716.pdf
CS8414
Technical Datasheet
http://www.cirrus.com/ftp/pubs/8413-4.pdf
CS8402
Technical Datasheet
http://www.cirrus.com/ftp/pubs/8401.pdf
MOTOROLA
LOCATION
DSP56362EVM User’s Manual
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3-1
Freescale Semiconductor, Inc.
COMPONENT DATASHEETS
Freescale Semiconductor, Inc...
Documentation
3-2
DSP56362EVM User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
SCHEMATICS
SECTION
4
SCHEMATICS
Freescale Semiconductor, Inc...
The schematics for the DSP56362EVM are included in the following pages. The bill of
material is listed in Section 5.
MOTOROLA
DSP56362EVM User’s Manual
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4-1
Section 4-2
A
B
C
+3.3V
+3.3V
D
+3.3V +3.3V
E
+3.3V
+3.3V
12
JP5
12
12
JP3 JP4
12
JP2
12
JP1
+3.3V
4
+5V
2
U1
MC34164
C160
C161
C162
C163
C164
C165
C166
C167
0.1uF
0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF
C6
0.1uF
Vccs1
26
GNDs1
9
25
GNDs0
96
87
8
Vccs0
GNDa3
GNDa2
81
86
Vcca2
GNDa1
75
80
Vcca1
74
Vcca0
GNDa0
GNDh
130
39
38
Vcch
120
129
Vccd3
GNDd3
GNDd2
112
119
Vccd2
GNDd1
104
111
Vccd1
GNDd0
66
103
Vccd0
GNDc1
65
Vccc1
GNDc0
48
58
47
46
57
Vccc0
Vccql0
Vccqh0
Vccql1
GNDq1
U2
DSP56362
Vccqh1
Vccql2
GNDq2
Vccqh2
Vccql3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
27
28 ADO
ACI
29
TIO0
142
138 TMS
53 TRST
141 DE
139 TCK
140 TDO
TDI
SDO0
SDO1
SDO2/SDI3
SDO3/SDI2
SDO4/SDI1
SDO5/SDI0
FST
FSR
SCKT
SCKR
HCKT
HCKR
4
5
6
7
10
11
12
13
14
15
16
17
MOSI
MISO
SCK
SS
HREQ
GNDq3
18
1 2
56
54
JP7
49
1 2
90
95
C22
0.1uF
126
127
72
73
76
77
78
79
82
83
84
85
88
89
92
93
94
97
98
99
+3.3V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
+3.3V
R10
10K
2
TDI
TDO
TCK
\TRST
TMS
\RESET
+3.3V +5V
JP12
BIT_CLK
MOTOROLA
ADO
256FS_CLK
R12
604
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
JP11
19
17
15
13
11
9
7
5
3
1
1
3
5
7
9
11
13
20
18
16
14
12
10
8
6
4
2
2
4
6
8
10
12
14
R11
10K
JP10
DA1_DSP
ML_DSP
\RESET
1
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
Size
A
Date:
A
3
91
R9
10K
+3.3V
FS_CLK
+3.3V
19
DA3_DSP
DA2_DSP
DA0_DSP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
4
20
+3.3V
DSP_CLK_3V
CLKOUT
+5V +3.3V
C17
0.1uF
JP6
GNDq0
143
144
1
2
3
2
4
6
8
\RESET
AA0
AA1
AA2
AA3
GNDp1
Vccp
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
137
136 MODA/IRQA
135 MODB/IRQB
134 MODC/IRQC
MODD/IRQD
44
70 RESET
69 AA0
51 AA1
50 AA2
AA3
52
68 CAS
67 RD
62 WR
63 TA
71 BR
64 BG
BB
\CAS
\RD
\WR
\TA
\BR
\BG
\BB
SDO0
SDO1
SDO2
SDO3
SDI1
SDI0
D1
R4 R5 R6 R7
10K 10K 10K 10K
100
101
102
105
106
107
108
109
110
113
114
115
116
117
118
121
122
123
124
125
128
131
132
133
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
43
41 H0
37 H2
36 H4
34 H5
33 H7
31 HA0
24 HA2
22 HOREQ/HOREQ
23 HRW
21 HACK/HACK
30 HDS/HDS
32 HCS
35 HA1
40 H6
42 H3
H1
+3.3V+3.3V+3.3V+3.3V
1
3
5
7
C5
0.1uF
C14
0.1uF
45
R3
2.7K
JP8
C3
0.1uF
C10
0.027uF
PCAP
C18
4.7uF
C9
0.1uF
C2
0.1uF
R2
10K
4
+
MOSI
MISO
SCK
\SS
\HREQ
1
IN RESET
C8 +
22uF
1
GND
2
C7
0.1uF
GNDp
R1
5K
S1
\RESET
3
+5V
C1
0.1uF
60
NC
55
59 EXTAL
61 CLKOUT
PINIT/NMI
DSP56362EVM USER’S MANUAL
Freescale Semiconductor, Inc...
L1
1uH
B
C
Title
Rev
DSP56362EVM DSP56362
Thursday, September 09, 1999
D
2.2.1
Sheet 1 of 10
E
MOTOROLA
A
B
C
D
E
AA0
AA1
\RD
\WR
AA2
4
+3.3V
U3
512k x 8 SRAM
13
6
O0
O1
O2
O3
O4
O5
O6
O7
32
16
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
2
3
4
5
14
15
16
17
20
21
22
23
24
32
33
34
35
1
18
U6
AT27LV010A_J
31
22 PGM
24 CE
OE
CE
VPP
1
7
8
11
12
25
26
29
30
OE
WE
6
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
13
D0
D1
D2
D3
D4
D5
D6
D7
VDD0
VDD1
9
27
CE
TP1
31
13
14
15
17
18
19
20
21
C31
0.1uF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
9
27
10
28
7
8
11
12
25
26
29
30
D0
D1
D2
D3
D4
D5
D6
D7
OE
WE
6
2
3
4
5
14
15
16
17
20
21
22
23
24
32
33
34
35
1
18
3
VDD0
VDD1
13
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CE
31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
OE
WE
31
C27
0.1uF
C30
0.1uF
GND0
GND1
7
8
11
12
25
26
29
30
D0
D1
D2
D3
D4
D5
D6
D7
VDD0
VDD1
GND0
GND1
9
27
C29
0.1uF
10
28
C28
0.1uF
+3.3V
C26
0.1uF
GND
+3.3V
D7
D6
D5
D4
D3
D2
D1
D0
GND0
GND1
C25
0.1uF
+3.3V
D23
D22
D21
D20
D19
D18
D17
D16
VCC
D15
D14
D13
D12
D11
D10
D9
D8
10
28
D7
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
14
15
16
17
20
21
22
23
24
32
33
34
35
1
18
DSP56362EVM USER’S MANUAL
Freescale Semiconductor, Inc...
4
3
U4
512k x 8 SRAM
U5
512k x 8 SRAM
+3.3V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
+3.3V
JP13
D0
D2
2
D4
D6
D8
D10
D12
D14
D16
D18
D20
D22
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
+3.3V
D1
D3
D5
D7
D9
D11
D13
D15
JP14
A0
A2
A4
A6
A8
A10
A12
A14
A16
1
3
5
7
9
11
13
15
17
19
D17
D19
+3.3V
R13
10K
JP15
A1
A3
A5
A7
A9
A11
A13
A15
A17
2
4
6
8
10
12
14
16
18
20
AA0
AA1
AA2
AA3
\RD
\WR
1
2
3
4
5
6
7
8
9 10
11 12
13 14
R14
10K
D21
D23
2
\BB
\BG
\BR
\TA
\CAS
CLKOUT
R15
10K
1
1
Size
A
B
C
Rev
DSP56362EVM EXTERNAL MEMORY
Date:
A
Title
Thursday, September 09, 1999
D
2.2.1
Sheet 2
of
E
10
Schematics
Section 4-3
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
Section 4-4
A
B
C
2
4
3
U7
MC68HC711E9
\RESET
R17
10K
R18
10K
R19
10K
R20
10K
2
2
1
S5
1
S4
1
S3
1
S2
2
2
\DA_MUTE
JP16
U9
GP1U58Y
DA_SEL2
RESET
IRQ
XIRQ
PB0
MODB
PB1
PB2
PA0
PB3
PA1
PB4
PA2
PB5
PA7
PB6
PA4
PB7
PA5
PA6
PC0
PA3
PC1
PC2
PE0
PC3
PE1
PC4
PE2
PC5
PE3
PC6
PE4
PC7
PE5
PE6
PD0/RXD
PE7
PD1/TXD
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
VDD
1
2
3
4
5
6
7
8
9
10
52
VRH 51
VRL
XT
EX
+5V
3
U8
LCD 20CHAR X 2LINE
42
41
40
39
38
37
36
35
DA_SEL0
DA_SEL1
ML_HC11
MC
MD
4
5 RS
6 R/W
E
9
10
11
12
13
14
15
16
7
8
9
10
11
12
13
14
20
21
22
23
24
25
D0
D1
D2
D3
D4
Vo
Vss
Vdd
D5
D6
D7
A
HC11_RXD
HC11_TXD
MISO
MOSI
SCK
\SS
K
+5V
R16
20K 1
2
8
7
17
19
18
2
34
33
32
27
30
29
28
31
43
45
47
49
44
46
48
50
3
3
1
2
15
R21
56
+5V
16
3
MODA
5
E 4
AS 6
R/W
VSS
+5V
+5V
1
OUT
26
GND
4
Y1
8MHZ
VCC
Freescale Semiconductor, Inc...
\HREQ
+5V
2
C32
0.1uF
2
Vcc
3
GND
1
Vout
DSP56362EVM USER’S MANUAL
2
E
+5V
4
3
D
1
1
MOTOROLA
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
Size
A
Date:
A
B
C
Title
Rev
DSP56362EVM MICROCONTROLLER AND LCD
Tuesday, September 21, 1999
D
Sheet 3
of
E
10
2.2.1
C
+5V
+5V
2
6
8
R25
71.5
+5V
C45
0.1uF
1
7
C139
2
3
4
9
Vd+
DGND
RXP
10
SW_EG1907
C140
0.01uF
+5V
M2
0
M1
1
M0
0
13
2
3
4
5
6
27
17
18
24
23
RXN
D2
43
DSP_CLK
1
RESET_MCU
26
SDATA 12
SCK 11
FSYNC
CS12/FCK
Cd/F1
Cc/F0
Cb/E2
Ca/E1
C0/E0
Ce/F2
M3
M2
M1
M0
26
41
1
C 14
U 28
VERF
25
ERF 15
CBL
SEL
SDI1
\RESET_MCU
19
MCK
31
32
33
34
35
4
3
38
23
22
20
19
16
C141
0.047uF
R93
1K
FORMAT
OUT, L/R, I2S COMPATIBLE
U11
ISPLSI2032-TQFP
11
I/O2 12
I/O3 13
I/O4 14
I/O5
25
I/O14 24
I/O13
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O16
I/O17
I/O18
I/O19
I/O20
I/O31
I/O30
I/O23
I/O21
I/O12
I/O11
I/O9
I/O8
I/O7
I/O10
DA0_PLD
DA1_PLD
DA2_PLD
DA3_PLD
37
I/O15
20
FILT
C38
0.1uF
I/O22
R26
1K
21
AGND
0.01uF
5
6
C136
0.1uF
22
Va+
9
10 I/O0
15 I/O1
I/O6
DA_SEL0
DA_SEL1
DA_SEL2
+5V
U26
CS8414A
16
S6
+5V
128FS_CLK
42
FS_CLK
44
BIT_CLK
2
256FS_CLK
3
36
21
5
Y0 29
Y1/RESET 40
GOE0
+5V
R28
10K
2
1 2
+5V
JP21
R29
10K
2
4
GND
VCC
Y2
24.576MHZ
+5V
OUT
1
3
+5V
JP22
2
4
1
2
3
4
5
6
7
8
SAMPLING RATE SELECT
JP23
2
GND
4
Y3
11.2896MHZ
R30
10K
JP24
3
1 2
OUT
3
1-2
ON
ON
OFF
OFF
3-4
ON
OFF
ON
OFF
FREQ
32KHZ
44.1KHZ
48KHZ
96KHZ
C46
0.01uF
1
JP25
Y4
8.192MHZ
2
GND
4
Section 4-5
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
1 2
OUT
3
Size
A
Date:
A
B
C
Title
Rev
DSP56362EVM S/PDIF I/O PLD
Tuesday, September 21, 1999
D
2.2.1
Sheet 4
of
E
10
Schematics
+5V
JP20
+5V +5V
1 2
VCC
DSP56362EVM USER’S MANUAL
1
GND
VCC0
4
2
5
+5V
C37
0.1uF
Vin
T2
1
8
+5V
4
+5V
Vcc
3
C135
0.1uF
J4
GP1F32R
J2
GP1F32T
39
C36
100pF
1
+5V
3
Vout
2
GND
2
8
J1
S/PDIF OUT
GND1
C40
0.1uF
1
Vcc
4
1
C39
0.1uF
C43
100pF
3
5
2
VCC
Freescale Semiconductor, Inc...
J3
S/PDIF IN
1
Vcc
GND
Y
5
4
Z
10
8
T1
R23
130
3
DE 1
R0
H/F
7
ADO
E
28
D1
A
4
D
C33
0.1uF
VCC1
9
B
R22
180
GND0
6
+5V
18
8 SDO
7 SDI
ISPEN
30
MODE
27
SCLK
U10
MAX1486
17
B
2
MOTOROLA
A
Section 4-6
A
B
C
D
E
2
+5V
+5V
M2
1
M1
0
M0 FORMAT
0 L/R, I2S COMPATIBLE
U13
CS8404A
23
22 M2
21 M1
M0
1
4 C7/C3
12 C6/C2
C9/C15
24
3 TRNPT/FC1
C1/FC0
SDO0
SDO1
SDO2
SDO3
2
4
6
8
JP27
BIT_CLK
FS_CLK
1
3
5
7
128FS_CLK
\RESET
6
7 SCK
8 FSYNC
SDATA
10
11 C/SBF
9 U
V
5
16 MCK
RST
VD+
GND
TXP
TXN
CBL/SBC
19
C47
0.1uF
18
R34
180
20
C48
0.1uF
T3
R35
130
17
1
5
4
8
J5
S/PDIF OUT
1
2
DSP56362EVM USER’S MANUAL
3
4
Freescale Semiconductor, Inc...
4
3
C49
100pF
15
2
PRO 14
EM0/C9 13
EM1/C8
+5V
+5V
C50
0.1uF
2
1
3
Vcc
J6
GP1F32T
Vin
GND
2
1
1
MOTOROLA
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
Size
A
Date:
A
B
C
Title
Rev
DSP56362EVM SECONDARY S/PDIF OUTPUT
Thursday, September 09, 1999
D
Sheet 5
of
E
10
2.2.1
MOTOROLA
A
B
C
D
E
+5VA
+
+
U14
PCM1800
C53
0.1uF
23
24
+
C55
4.7uF
2
3
+
J7
RCA_2X2
2
5
VREF1
FMT0
REFCOM
FMT1
BYPAS
1
OUT_LEFT
OUT_RIGHT
+5VA
R40
100K
5
\RESET
6
12
FS_CLK
13
BIT_CLK
14
256FS_CLK
16
C54
0.1uF
17
+5VA
8
9
3
7
VINL
DOUT
C58
1uF
18
VREF2
VINR
CINNR
RSTB
CINPR
FSYNC
CINNL
LRCK
CINPL
BCK
SYSCLK
11
4
DGND
R39
100K
1
6
C56
4.7uF
AGND
MODE0
RIGHT IN
C57
1uF
VDD
MODE1
3
4
VCC
C52
10uF
15
19
SDI0
C59
470pF
20
21
22
C60
470pF
10
LEFT IN
+
2
+5VA
C51
10uF
+
DSP56362EVM USER’S MANUAL
3
4
Freescale Semiconductor, Inc...
4
2
1
1
Size
A
Date:
A
B
C
Title
Rev
DSP56362EVM ANALOG INPUT
Thursday, September 09, 1999
D
2.2.1
Sheet 6 of 10
E
Schematics
Section 4-7
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
B
+
10uF
10uF
C97
C98
10uF
10uF
+
16
C155
10uF
C94
C96
+
11
+
+
13
18
12
NC0 17
NC1
6
5
4
+
C108
0.1uF
+
16
13
C157
10uF
C110
C112
C113
C114
18
11
10uF
10uF
\RESET
\DA_MUTE
+
R69
100
7
R70
2.7K
RIGHT SURROUND OUT
9
LEFT OUT
8
RIGHT OUT
-5V
R73
3.9K
+5VA
C107
1uF
+
U23A
MC33078
2
3
R75
2.7K
3
R74
100
8
C106
330pF
1
C109
1uF
-5V
C115
330pF
U23B
MC33078
R79
3.9K
5
+5VA
R80
100
7
R81
2.7K
-5V
2
19
9
C121
1uF
10
R82
10K
C122
330pF
U25A
MC33078
15
14
C124
0.1uF
16
13
18
11
+
C159
10uF
C126
C128
10uF
10uF
C129
C130
10uF
10uF
R83
5.6K
R84
3.9K
C127
2700pF
R88
10K
12
NC0 17
NC1
R89
5.6K
C134
2700pF
+5VA
2
3
R86
2.7K
C123
1uF
R85
100
1
C125
1uF
-5V
C131
330pF
U25B
+5VA
MC33078
6
1
R90
3.9K
5
R91
100
7
R92
2.7K
1
MOTOROLA
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
-5V
Size
A
B
C
Title
Rev
DSP56362EVM ANALOG OUTPUTS
Date:
A
LEFT SURROUND OUT
5
7
C120
1uF
+
VCC2L
AGND2L
VCC2R
28
27 ML/IIS
26 MC/DM1 AGND2R
MD/DM0
VCC1
2
AGND1
1 DIN
3 LRCIN
5 BCKIN
XTI
VOUTL
21
23 ZERO
22 CS/IWO VOUTR
25 RST
MUTE
EXTL
24
MODE
EXTR
6
4 XTO
CLKO
DA_MODE
DGND
5
+
SDO0
FS_CLK
BIT_CLK
256FS_CLK
DA3_DSP
DA3_PLD
VDD
+5VA
20
+
MC
MD
DA2_DSP
DA2_PLD
R78
5.6K
C118
2700pF
+
DA1_DSP
DA1_PLD
7
R72
5.6K
C111
2700pF
R77
10K
+
DA0_DSP
DA0_PLD
6
6
U24
PCM1716
8
6
10uF
10uF
12
NC0 17
NC1
+
C119
0.1uF
4
4
4
14
+5VA
+
2
R68
3.9K
15
3
2
1
C158
10uF
R67
5.6K
U21B
MC33078
+
DA_MODE
SUBWOOFER OUT
+5VA
8
9
8
7
C99
330pF
4
\RESET
\DA_MUTE
6
4 XTO
CLKO
12
11
10
R66
10K
R71
10K
C105
1uF
10
+
15
14
13
9
+
SDO1
FS_CLK
BIT_CLK
256FS_CLK
JP31
CENTER OUT
2
19
+
MC
MD
3
1
+
28
27 ML/IIS
26 MC/DM1 AGND2R
MD/DM0
VCC1
2
AGND1
1 DIN
3 LRCIN
5 BCKIN
XTI
VOUTL
21
23 ZERO
22 CS/IWO VOUTR
25 RST
MUTE
EXTL
24
MODE
EXTR
+
VCC2R
+
AGND2L
C93
1uF
-5V
C102
2700pF
C104
1uF
J8
RCA_3X2
R63
100
1
R64
2.7K
-
VCC2L
DGND
C91
1uF
+
VDD
C95
2700pF
3
-
7
+5VA
20
R62
3.9K
+
+
DSP56362EVM USER’S MANUAL
U22
PCM1716
8
R61
5.6K
2
4
+
C92
0.1uF
+5VA
C103
0.1uF
+5VA
U21A
MC33078
8
+
14
DA_MODE
C156
10uF
C90
330pF
+
R60
10K
C89
1uF
10
-
6
4 XTO
CLKO
9
15
+
R95
0
19
-
AGND2L
+
+5V
DA3_CS
ML_DSP
ML_HC11
E
C88
1uF
+
DGND
+5VA
20
-
VCC2L
+
7
VDD
VCC2R
28
27 ML/IIS
26 MC/DM1 AGND2R
MD/DM0
VCC1
2
AGND1
1 DIN
3 LRCIN
BCKIN
5
XTI
VOUTL
21
23 ZERO
22 CS/IWO VOUTR
25 RST
MUTE
EXTL
24
MODE
EXTR
SDO2
FS_CLK
BIT_CLK
256FS_CLK
Freescale Semiconductor, Inc...
U20
PCM1716
8
ML
MC
MD
3
D
-
C87
0.1uF
4
C
+5VA
+
C154
10uF
+
Section 4-8
A
Thursday, September 09, 1999
D
2.2.1
Sheet 7
of
E
10
MOTOROLA
A
B
C
D
E
+5VA
6
4 XTO
CLKO
+
C72
1uF
R49
10K
C74
330pF
U19A
MC33078
15
18
11
C81
C82
R50
5.6K
10uF
10uF
R51
3.9K
10uF
10uF
R55
10K
12
NC0 17
NC1
2
3
R53
2.7K
C79
2700pF
C83
330pF
C86
2700pF
R57
3.9K
1
R52
100
OUT_LEFT
C77
1uF
3
-5V
+5VA
U19B
MC33078
6
R56
5.6K
C75
1uF
4
C153
10uF
C78
C80
+
+
+
16
13
C76
0.1uF
+
14
+5VA
+
C73
1uF
10
8
9
+
19
+
DA_MODE
AGND2L
VCC2R
28
27 ML/IIS
26 MC/DM1 AGND2R
MD/DM0
VCC1
2
AGND1
1 DIN
3 LRCIN
BCKIN
5
XTI
VOUTL
21
23 ZERO
22 CS/IWO VOUTR
25 RST
MUTE
EXTL
24
MODE
EXTR
+5VA
20
5
-
DA3_CS
\RESET
\DA_MUTE
DGND
VCC2L
R58
100
7
OUT_RIGHT
+
SDO3
FS_CLK
BIT_CLK
256FS_CLK
7
VDD
-
ML
MC
MD
U18
PCM1716
8
+
C152
10uF
C71
0.1uF
+
2
NOTE:
AUXILIARY ANALOG OUTPUT
+
DSP56362EVM USER’S MANUAL
3
4
Freescale Semiconductor, Inc...
4
R59
2.7K
-5V
2
1
1
Size
A
Date:
A
B
C
Title
Rev
DSP56362EVM AUXILIARY ANALOG OUTPUTS
Thursday, September 09, 1999
D
Sheet 8
of
E
2.2.1
10
Schematics
Section 4-9
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
Section 4-10
A
B
C
D
E
+3.3V
U31
NC7SZ125
1
2
DSP_CLK
3
5
C61
0.1uF
GND
Y
4
DSP_CLK_3V
4
R44
10K
R43
10K
+5V
+5V
R96
10K
8
9
10
11
12
13
14
15
R45
10K
41
42 RESET
IRQ
28
TDO
37
OSC1
\RESET_MCU
+5V
C64
1uF
1
C1+
2
GND
VSS
18
C69
1uF
C66
22pF
R46
10K
27
17
Vss
C67
22pF
RESET_MCU
2
12
D03 11
D13
1
3
5
HC11_TXD
+
P1
RDI
3
+5V
32
SS 31
SCK 30
MOSI 29
MISO
20
16
D01 15
D11
14
D02 13
D12
U17
145407
4
5
9
4
8
3
7
2
6
1
C2+
5
6 RX1
TX1
7
8 RX2
TX2
9
10 RX3
TX3
C1-
TCK
TDO
TDI
\TRST
\RESET
TMS
Y5
3.6864MHZ
19
+
C2-
VCC
17
3
VDD
R48
10K
C68
1uF
+
+5V
26
25
24
23
21
20
19
18
R47
10M
C65
1uF
+
C63
1uF
35
TCAP 33
TCMP 43
Vpp 34
PD7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
OSC2
+5V
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
U16
MC68HC705C8A-QFP
36
+5V
7
6
5
4
3
2
1
44
Vdd
38
C62
0.1uF
+
2
VCC
A
+5V
+
DSP56362EVM USER’S MANUAL
3
Freescale Semiconductor, Inc...
4
OE
2
4
6
HC11_RXD
JP28
C70
1uF
1
1
MOTOROLA
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
Size
A
Date:
A
B
C
Title
Rev
DSP56362EVM RS-232/OnCE INTERFACE
Thursday, September 09, 1999
D
Sheet 9
of
E
2.2.1
10
MOTOROLA
A
B
C
D
E
4
+5V
-5V
1
2
3
D5
FM4001
D7
FM4001
FM4001
L2
3
C142
1000uF
+
C143
0.33uF
VOUT
2
VIN
GND
1
C144
0.33uF
+
2
+
VIN
GND
FM4001
D6
U27
LT1085
1
D4
C149
0.33uF
+
2
P2
Power Jack
+5VA
2
1
VOUT
C145
47uF
+
+
3
+3.3V
P3
Power Terminal
C146
47uF
+
C147
47uF
+
DSP56362EVM USER’S MANUAL
Freescale Semiconductor, Inc...
4
3
L3
C148
470uF
C150
0.1uF
3
L4
L5
R94
1K
U28
MC7805
U29
NMF0505_SIP
D8
1
2
DC +VREG 6
Vin
GND
DC
0V
4
2
PCB Mounting Holes
M2 M3 M4
M1
.125
.125 .125 .125
1
1
Size
A
Date:
A
B
C
Title
Rev
DSP56362EVM POWER SUPPLY
Thursday, September 09, 1999
D
2.2.1
Sheet 10
of
E
10
Schematics
Section 4-11
MOTOROLA
IMAGING AND ENTERTAINMENT SOLUTIONS
DIGITAL AUDIO APPLICATIONS
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Section 4-12
DSP56362EVM USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
BILL OF MATERIALS
Evaluation Module Parts
SECTION
5
BILL OF MATERIALS
Freescale Semiconductor, Inc...
5.1
EVALUATION MODULE PARTS
The following table contains information on the parts and devices in the Evaluation Module.
Contact information for suppliers of key devices is also included in Table 5-1.
Table 5-1 Evaluation Module Bill of Materials
Reference Designator
Description
Manufacturer
MFG P/N
C46, C139, C140, C161, C163, C165,
C167
0.01uF, CHIPCAP 0805, 50V/10% TOL
PANASONIC
ECU-V1H103KBG
C1, C2, C3, C5, C6, C7, C9, C14, C17,
C22, C25, C26, C27, C28, C29, C30, C31,
C32, C33, C37, C38, C39, C40, C45, C47,
C48,C50, C53, C54, C61, C62, C71,C76,
C87, C92, C103, C108, C119, C124, C135,
C136, C150, C160, C162, C164, C166
0.1uF, CHIPCAP 0805, 50V/20% TOL
AVX
08055E104MATMA
C8
22uF, TANTALUM ELECTROLYTIC
SMD, 6.3V/EIA SIZE B
PANASONIC
ECS-T0JX226R
C10
0.027uF, CHIPCAP 0805, 50V/10%
TOL
PANASONIC
ECU-V1H273KBX
C18, C55, C56
4.7uF, TANTALUM ELECTROL.
SMD, 6.3V/EIA SIZE A
PANASONIC
ECS-T0JY475R
C36, C43, C49
100pF, CHIPCAP 0805, 50V/5% TOL
PANASONIC
ECU-V1H101JCG
C141
0.047uF, CHIPCAP 0805, 50V/10%
TOL
XICON
CC501Z473M
C51, C52, C78, C80, C81, C82, C94, C96,
C97, C98, C110, C112, C113, C114, C126,
C128, C129, C130, C152, C153, C154,
C155, C156, C157, C158, C159
10uF, TANTALUM ELECTROL. SMD,
6.3V/EIASIZE A
PANASONIC
ECS-T0JY106R
C57, C58, C63, C64, C65, C68, C69, C70,
C72, C73, C75, C77, C88, C89, C91, C93,
C104, C105,C107, C109, C120, C121,
C123,C125
1uF, CHIPCAP 1206, 16V/20% TOL
PANASONIC
ECU-V1H471JCX
C59, C60
470pF, CHIPCAP 0805, 50V/5% TOL
PANASONIC
ECU-V1H471JCX
C66, C67
22pF, CHIPCAP 1206, 50V/5% TOL
PANASONIC
ECU-V1H220JCN
MOTOROLA
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5-1
Freescale Semiconductor, Inc.
BILL OF MATERIALS
Evaluation Module Parts
Table 5-1 Evaluation Module Bill of Materials
Freescale Semiconductor, Inc...
Reference Designator
Description
Manufacturer
MFG P/N
C74, C83, C90, C99, C106, C115, C122,
C131
330pF, CHIPCAP 0805, 50V/10% TOL
PANASONIC
ECU-V1H331KBN
C79, C86, C95, C102, C111, C118, C127,
C134
2700pF, CHIPCAP 0805, 50V/10%
TOL
PANASONIC
ECU-V1H272KBN
C148
470uF, RADIAL ALUMINUM
ELECTROLYTIC, 10V
XICON
XRL10V470
C142
1000uF, MINI ALUM ELECTROL,
16V/AXIAL/0.394X0.984
XICON
XAH16V1000
C143, C144, C149
0.33uF. CHIPCAP 1206, 35V/20% TOL
PANASONIC
ECS-T1VY334R
C145, C146, C147
47uF, SUBMINI ALUM ELECROL,
10V/RADIAL/5X7
XICON
MLRL10V47
D1
YELLOW LED, SMD 1206
QT
OPTOELECTR
ONICS
QTLP650D-3
D2
RED LED, SMD 1206
QT
OPTOELECTR
ONICS
QTLP650C-2
D8
GREEN LED, SMD 1206
QT
OPTOELECTR
ONICS
QTLP650C-4
D4, D5, D6, D7
RECTIFIER, 1.0 AMP SMD
RECTRON
FM4001
XXU8
DOUBLE ROW 16-PIN FEMALE
HEADER, RECEPTACLE FOR U8
BERG
68683-608
JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP20,
JP21, JP23, JP25
SINGLE ROW 2 PIN HEADER
BERG
86001-402
JP8, JP27
DOUBLE ROW 8 PIN HEADER
BERG
67997-408
JP10, JP15
DOUBLE ROW 14 PIN HEADER
BERG
67997-414
JP11, JP14
DOUBLE ROW 20 PIN HEADER
BERG
67997-420
JP12
DOUBLE ROW 50 PIN HEADER
BERG
67997-450
JP13
DOUBLE ROW 36 PIN HEADER
BERG
67997-436
JP16
SINGLE ROW 10 PIN HEADER
BERG
86001-410
JP35
Not Populated
JP22
SINGLE ROW 8 PIN HEADER
BERG
86001-408
JP24
DOUBLE ROW 4 PIN HEADER
BERG
67997-404
JP28
DOUBLE ROW 6 PIN HEADER
BERG
67997-406
5-2
DSP56362EVM User’s Manual
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MOTOROLA
Freescale Semiconductor, Inc.
BILL OF MATERIALS
Evaluation Module Parts
Table 5-1 Evaluation Module Bill of Materials
Reference Designator
Description
JP31
Manufacturer
MFG P/N
TRIPLE ROW 15 PIN HEADER
BERG
68702-415
J1, J3, J5
RCA JACK
VIMEX
SCJ-0358B
J2, J6
OPTICAL TRANSMIT CONNECTOR
SHARP
GP1F32T
J4
OPTICAL RECEIVE CONNECTOR
SHARP
GP1F32R
J7
RCA JACK 2X2
VIMEX
JA0400721G
J8
RCA JACK 3X2
VIMEX
JA0600731G
L1
1uH INDUCTOR, SMD/2.5X3.2
TOKO
TKS1025CT
L2, L3, L4, L5
FERRITE BEAD
FUTURE
BL01RN1-A62
XU6
SOCKET FOR U6, 32P PIN
PLCC/THRU HOLE
MOUSER
151-1033
XU7
SOCKET FOR U7, 52 PIN
PLCC/THRU HOLE
MOUSER
151-1053
P1
DB9 CONNECTOR, RT ANGLE/PCB
MOUNT
MOUSER
152-3409
P2
2.1MM POWER CONNECTOR
SWITCHCRAF
T
93F7716
P3
2 PIN TERMINAL BLOCK
AUGAT
2SV-02
R1
5.1K, CHIP RES 0805, 1/10WATT 5%
PANASONIC
ERJ-6GEYJ512V
R2, R4, R5, R6, R7, R9, R10, R11, R13,
R14, R15, R17, R18, R19, R20, R28, R29,
R30, R43, R44, R45, R46, R48, R49, R55,
R60, R66, R71, R77, R82, R88, R96
10K, CHIP RES 0805, 1/10WATT 5%
PANASONIC
ERJ-6GEYJ103V
R3, R53, R59, R64, R70, R75, R81, R86,
R92
2.7K, CHIP RES 0805, 1/10WATT 5%
PANASONIC
ERJ-6GEYJ272V
R12
604, CHIP RES 0805,1/10WATT 1%
PANASONIC
ERJ-6ENF6040V
R22, R34
182, CHIP RES 0805,1/8WATT 1%
PANASONIC
ERJ-6ENF1820V
R23, R35
127, CHIP RES 0805, 1/8WATT 1%
PANASONIC
ERJ-6ENF1270V
R95
0, CHIP RES 0805, 1/10WATT 5%
PANASONIC
ERJ-6GEY0R00V
R25
71.5, CHIP RES 0805, 1/10WATT 1%
PANASONIC
ERJ-6ENF71R5V
R26, R93, R94
1K, CHIP RES 0805, 1/10WATT 5%
PANASONIC
ERJ-6GEYJ102V
R39, R40
100K, CHIP RES 0805, 1/10WATT 5%
PANASONIC
ERJ-6GEYJ104V
Freescale Semiconductor, Inc...
removed
MOTOROLA
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5-3
Freescale Semiconductor, Inc.
BILL OF MATERIALS
Evaluation Module Parts
Freescale Semiconductor, Inc...
Table 5-1 Evaluation Module Bill of Materials
Reference Designator
Description
R50, R56, R61, R67, R72, R78, R83, R89
5.62K, CHIP RES 0805, 1/10WATT 1%
PANASONIC
PERJ-6ENF5621V
R51, R57, R62, R68, R73, R79, R84, R90
3.92K, CHIP RES 0805, 1/10WATT 1%
PANASONIC
ERJ-6ENF3921V
R52, R58, R63, R69, R74, R80, R85, R91
100, CHIP RES 0805, 1/10WATT 1%
PANASONIC
ERJ-6ENF101V
R47
10M, CHIP RES 0805, 1/10WATT 5%
PANASONIC
ERJ-6GEYJ106V
R21
56, CHIP RES 0805, 1/10WATT 5%
PANASONIC
ERJ-6GEYJ560V
S6
SLIDE SWITCH DPDT
E-SWITCH
EG2209
S1, S2, S3, S4, S5
6MM PUSHBUTTON SWITCH
PANASONIC
EVQ-QS205K
R16
TRIMPOT 20K
PANASONIC
EVN-D8AA03B24
T1, T2, T3
96KHZ DIGITAL TRANSFORMER
SCIENTIFIC
CONVERSION
SC979-03
U1
UNDERVOLTAGE SENSOR
MOTOROLA
MC34164D-5
U2
DSP, 144PIN/TQFP *please see note
#68
MOTOROLA
DSP56362
U3, U4, U5
128KX8 SRAM, 3.3V/400MIL
GSI
TECHNOLOG
Y
GS71108J-10
U6
128KX8 EPROM, 3.3V/32 PIN PLCC,
*please see note #70
ATMEL
AT27LV010A-15JC
U7
8-BIT MICROCONTROLLER, 52 PIN
PLCC *please see note #71
MOTOROLA
MC68HC711E20VFN2
U8
LCD 20CHAR X 2LINE
POWERTIP
PC2002LRU-AEA-B
U9
Not Populated
U10
MAX1486
MAXIM
MAX1486CUB
U11
PLD (See PLD Equations following this
BOM)
LATTICE
ISPLSI2032-110LT44
U12
Not populated
U13
DIGITAL AUDIO TRANSMITTER
CRYSTAL
CS8404A-CS
U14
20-BIT A/D CONVERTER,
24-PIN/SSOP
BURR-BROWN
PCM1800
U31
BUFFER WITH 3 STATE OUTPUT,
SOT23-5
FAIRCHILD
NC7SZ125M5
U16
8-BIT MICROCONTROLLER
MOTOROLA
MC68HC705C8ACFB
U17
RS-232 TRANSCEIVER
MOTOROLA
MC145407DW
5-4
Manufacturer
DSP56362EVM User’s Manual
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MFG P/N
MOTOROLA
Freescale Semiconductor, Inc.
BILL OF MATERIALS
Evaluation Module Parts
Table 5-1 Evaluation Module Bill of Materials
Freescale Semiconductor, Inc...
Reference Designator
Description
Manufacturer
MFG P/N
U18, U20, U22, U24
DELTA-SIGMA D/A CONVERTER
BURR-BROWN
PCM1716
U19, U21, U23, U25
OP-AMP, SO-8
BURR-BROWN
BBOPA2134UA
U26
DIGITAL AUDIO RECEIVER
CRYSTAL
CS8414-CS
U27
3.3V REGULATOR, TO-220
LINEAR
TECH.
LT1085CT-3.3
U28
5V REGULATOR, TO-220
MOTOROLA
MC7805ACT
U29
DC-DC CONVERTER
NEWPORT
TECH.
NMF0505S
U30
Not Populated
Y1
8MHZ OSCILLATOR, SMD
MMD
MI5050H-8MHZ
Y2
24.576MHZ OSCILLATOR, SMD
MMD
MI5050H-24.576MHZ
Y3
11.2896MHZ OSCILLATOR, SMD
MMD
MI5050H-11.2896MHZ
Y4
8.192MHZ OSCILLATOR, SMD
MMD
MI5050H-8.192MHZ
Y5
3.6864MHZ CRYSTAL, HC49
ECS
X403
Mounting hardware for ‘U8’ and standoffs
for the four corners of the PC board.
Standoffs
H.H. Smith
30F1463
Mounting hardware for ‘U8’ and standoffs
for the four corners of the PC board.
Screws
Waldom
FN-817-C
XU28
Heatsink for U28 T0-220, L=0.75,
W=0.520, H=0.500 (above dimensions
are in inches)
AAVID
Thermal
Technologies
Inc.
577202B00000
XU8
DOUBLE ROW 16-PIN MALE
HEADER MOUNTS TO BOTTOM
SIDE OF U8 LCD
BERG
68683-608
SHUNTS
SHUNT CONN., 2 POSITION
3M
929955-06
Note #68. This part is mounted on a socket
and the part information for the socket is
given in the following columns
Yamaichi 144 pin TQFP socket
Yamaichi
Electronics
IC149-144-045-S5
Note #70. This part is mounted on a socket
and the part information for the socket is
given in the following columns
Mouser PLCC socket, 32 pin
Mouser
151-1533
Note #71. This part is mounted on a socket
and the part information for the socket is
given in the following columns. The
programmed part in installed in the socket.
Mouser PLCC socket, 52 pin
Mouser
151-1553
MOTOROLA
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5-5
Freescale Semiconductor, Inc.
BILL OF MATERIALS
PLD Equations
5.2
PLD EQUATIONS
Freescale Semiconductor, Inc...
Declarations
"inputs
SEL1..SEL0
CLK8M
CLK11M
CLK24M
CS_LRCK
CS_SCK
RESET_MCU
DA_SEL1..DA_SEL0
DA_SEL2
CS_MCK
JUMP
"outputs
FS_CLK
BIT_CLK
RESET_MCU_
used instead.
FS_CLK256
FS_CLK128
DA3_PLD
DA2_PLD
DA1_PLD
DA0_PLD
DSP_CLK
"nodes
CLK12M
div3..div0
FM_CLK256
scale7..scale0
DIV4
DIV64
DIV256
FM_CLK256B
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
34,35;
33;
32;
31;
20; "FS CLOCK from the CS8414
22; "BIT CLOCK from the CS8414
1;
10,9;
15;
19; "256 clock from the Crystal clock chip
16; "Jumper selection ON=AD : OFF=SPDiA
pin 42 istype ’com’;
pin 44 istype ’com’;
pin 4; " Pin 5 in hardware but this pin can not be used.Oin 4 is
pin
pin
pin
pin
pin
pin
pin
2 istype ’com’; "sync buffered version
24 istype ’com’;
14;
13;
12;
11;
43; "output clk8m divided by 8 (dsp_clk)
node istype
node istype
node istype
node istype
node;
node;
node;
node istype
’reg_d’;
’reg_d’;
’com,keep,retain’;
’reg_d’;
’keep,retain’;
"sets
DIVIDE = [div3..div0];
FS_GEN = [scale7..scale0];
"constants
h,l,x,z,c = 1,0,.x.,.z.,.c.;
5-6
DSP56362EVM User’s Manual
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Freescale Semiconductor, Inc.
BILL OF MATERIALS
PLD Equations
"plsi properties
plsi
plsi
plsi
plsi
property
property
property
property
’Y1_AS_RESET OFF’;
’ENP FS_CLK128 npath1’;
’PRESERVE FM_CLK256’;
’PRESERVE FM_CLK256B’;
Freescale Semiconductor, Inc...
Equations"
Internal Generation of FS/Bit clock when NO SPDiA is available
FS_GEN := FS_GEN + 1;
FS_GEN.CLK = !FM_CLK256B;
DIV256=scale7;
DIV64 = scale5;
DIV4 = scale1;
" Sync buffered version of FS clock
FS_CLK = (JUMP & DIV256) # (!JUMP & CS_LRCK);
" Sync buffered version of BIT clock
BIT_CLK = (JUMP & DIV4) # (!JUMP & CS_SCK);
" Buffered reset signals
RESET_MCU_ = !RESET_MCU;
"Multiplexed clock outputs : drives fs_CLK256 when Crystal not SELected
FM_CLK256 = ((!SEL1 & !SEL0 & CLK8M)
# (!SEL1 & SEL0 & CLK11M)
# ( SEL1 & !SEL0 & CLK12M)
# ( SEL1 & SEL0 & CLK24M));
FM_CLK256B =
#
#
#
((!SEL1 & !SEL0 & CLK8M)
(!SEL1 & SEL0 & CLK11M)
( SEL1 & !SEL0 & CLK12M)
( SEL1 & SEL0 & CLK24M));
" SDF Rcvr PLL input to the 256/128 outputs
FS_CLK256 = (JUMP & FM_CLK256) # (!JUMP & CS_MCK);
FS_CLK128 = ( FS_CLK128 $ ((JUMP & FM_CLK256 & !FS_CLK256) # (!JUMP &CS_MCK &
!FS_CLK256)));
" Divide by 2 for the Clock input Mux
CLK12M := !CLK12M;
CLK12M.CLK = CLK24M;
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Freescale Semiconductor, Inc.
BILL OF MATERIALS
PLD Equations
"Divide by 8 for the 8 Mhz Clock input with direct output path
DIVIDE := DIVIDE + 1;
DIVIDE.CLK = CLK8M;
//DSP_CLK = div3;
DSP_CLK = CLK8M;
"If no jumper at J20 and DIR is on thenY2-Y4
"are used to generate the all the bit clocks
"for the AD converters.
// XTI is not used in the rev 2.2 of the EVM - Mithra 08/24/99
Freescale Semiconductor, Inc...
//XTI = FM_CLK256 & !JUMP;
" 2 to 4
!DA3_PLD
!DA2_PLD
!DA1_PLD
!DA0_PLD
Decoder
= ((!DA_SEL2
= ((!DA_SEL2
= ((!DA_SEL2
= ((!DA_SEL2
&
&
&
&
DA_SEL1
DA_SEL1
!DA_SEL1
!DA_SEL1
& DA_SEL0) # (DA_SEL2
& !DA_SEL0) # (DA_SEL2
& DA_SEL0) # (DA_SEL2
& !DA_SEL0) # (DA_SEL2
&
&
&
&
!DA_SEL1
!DA_SEL1
!DA_SEL1
!DA_SEL1
&!DA_SEL0));
&!DA_SEL0));
&!DA_SEL0));
&!DA_SEL0));
END
5-8
DSP56362EVM User’s Manual
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RUNNING THE PASS-THROUGH CODE
Pass-Through Operation
SECTION
6
RUNNING THE PASS-THROUGH CODE
Freescale Semiconductor, Inc...
The Evaluation Module includes an HC11 with the pass-through files programmed in the
EPROM. The pass-through software allows users to input and output audio to the Evaluation
Module without loading the files through the OnCE (stand-alone mode).
6.1
PASS-THROUGH OPERATION
The main loop of the digital.asm and analog.asm programs serve as a reference guide
on how to pass data into and out of the EVM.
6.1.1
RECEIVE INTERRUPT SERVICE ROUTINES
The receive interrupt service routine esai_rx_isr moves the left data word from the receive
data register RXn (RX0 or RX1) into the receive left data buffer RX_BUFF_BASE and
moves the right data word from the receive data register RXn into the receive right data buffer
RX_BUFF_BASE+1. The pointer to the RX_BUFF_BASE has modulo of 2, so it alternates
between the left and right receive buffers.
If the serial receive shift register SDI0 or SDI1 is filled and ready to transfer to the receiver
data register RXn and RXn is already filled, then the Receiver Overrun Error Flag (ROE) is
set and the receive with exception interrupt service routine esai_rxe_isr is called. This routine
clears the ROE bit.
The receive last slot interrupt service routine esai_rxls_isr resets the buffer pointer to
RX_BUFF_BASE in case the pointer is corrupted after the last slot of the frame. For example,
after the right data is received.
MOTOROLA
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6-1
Freescale Semiconductor, Inc.
RUNNING THE PASS-THROUGH CODE
Pass-Through Operation
X MEMORY
RX0 or RX1
RX_BUFF_BASE
(LEFT)
RX_BUFF_BASE+1
(RIGHT)
Freescale Semiconductor, Inc...
Figure 6-1 Receive Input Buffer
esai_rxe_isr
; ESAI RECEIVE WITH EXCEPTION ISR
bclr
#7,x:M_SAISR; Read SAISR to clear receive
; overrun error flag
esai_rx_isr
; ESAI RECEIVE ISR
move
r0,x:(r6)+ ; Save r0 to the stack
move
m0,x:(r6)+ ; Save m0 to the stack
move
#1,m0 ; Modulus 2 buffer
move
x:RX_PTR,r0 ; Load the pointer to the rx buffer
nop
jset#$6,x:M_SAISR,LeftSlot
bset#RightReceive,x:flags
movep
x:M_RX1,x:(r0)+; Receive from RX1 in this case
move
r0,X:RX_PTR
move
x:-(r6),m0 ; Restore m0
move
x:-(r6),r0 ; Restore r0
rti
esai_rxls_isr
move
move
move
move
; ESAI RECEIVE LAST SLOT ISR
r0,x:(r6)+ ; Save r0 to the stack
#RX_BUFF_BASE,r0; Reset rx buffer pointer just in
; case it was corrupted
r0,x:RX_PTR ; Update rx buffer pointer
x:-(r6),r0 ; Restore r0rti
Figure 6-2 Receive Interrupt Service Routines
6-2
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RUNNING THE PASS-THROUGH CODE
Pass-Through Operation
6.1.2
TRANSMIT INTERRUPT SERVICE ROUTINES
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The transmit interrupt service routine moves the left data word from the transmit left data
buffer TX_BUFF_BASEinto the transmit data register TXn (TX0, TX1, TX2 or TX3) and
moves the right data word from the transmit right data buffer TX_BUFF_BASE+1 into the
transmit data register TXn. The pointer to the TX_BUFF_BASE has modulo of 2 so it
alternates between left and right transmit buffers.
If the serial receive shift register SDI0 or SDI1 is filled and ready to transfer to the receiver
data register RXn and RXn is already filled, then the Receiver Overrun Error Flag (ROE) is
set and the receive with exception interrupt service routine esai_rxe_isr is called. This routine
clears the ROE bit.
The receive last slot interrupt service routine esai_rxls_isr resets the buffer pointer to
RX_BUFF_BASE in case the pointer is corrupted after the last slot of the frame. For example,
after the right data is received.
X MEMORY
TX_BUFF_BASE
(LEFT)
TX0, TX1, TX2 or TX3
TX_BUFF_BASE+1
(RIGHT)
Figure 6-3 Transmit Output Buffer
esai_txe_isr
bclr
; ESAI TRANSMIT WITH EXCEPTION ISR
#14,x:M_SAISR ; Read SAISR to clear transmit;
underrun error flag
esai_tx_isr
; ESAI TRANSMIT ISR
mover0,x:(r6)+ ; Save r0 to the stack
movem0,x:(r6)+ ; Save m0 to the stack
move #1,m0 ; Modulus 2 buffer
movex:TX_PTR,r0 ; Load the pointer to the Tx buffer
nop
movep
movep
movep
movep
move
move
move
esai_txls_isr
MOTOROLA
x:(r0),x:M_TX0; Transmit to TX0 in this case
x:(r0),x:M_TX1
x:(r0),x:M_TX2
x:(r0)+,x:M_TX3
r0,x:TX_PTR ; Update tx buffer pointer
x:-(r6),m0 ; Restore m0
x:-(r6),r0 ; Restore r0rti
; ESAI TRANSMIT LAST SLOT ISR
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RUNNING THE PASS-THROUGH CODE
Pass-Through Operation
move
move
move
move
r0,x:(r6)+ ; Save r0 to the stack
#TX_BUFF_BASE,r0 ; Reset pointer
r0,x:TX_PTR ; Reset tx buffer pointer just in
; case it was corrupted
x:-(r6),r0rti
Freescale Semiconductor, Inc...
Figure 6-4 Transmit Interrupt Service Routines
6-4
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RUNNING THE PASS-THROUGH CODE
Pass-Through Operation
6.1.3
MAIN LOOP
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Bit 6 of the ESAI Status Register (SAISR) which is the receive frame sync flag (RFS) is
polled to wait for a frame sync to occur. When the frame sync occurs, the contents of the input
buffers RX_BUFF_BASE and RX_BUFF_BASE+1 are copied to accumulators a and b.
Users can insert additional processing code at this point. If no processing is required, the
contents of accumulators a and b are copied to the output buffers TX_BUFF_BASE and
TX_BUFF_BASE+1. The program jumps back to the beginning of the loop for the next
sample.
LOOP
jclr #RightRecieve,X:flags,*
bclr #RightRecieve,X:flags
move x:RX_BUFF_BASE,a ;receive left
move x:RX_BUFF_BASE+1,b ;receive right
move a,x:TX_BUFF_BASE ;transmit left
move b,x:TX_BUFF_BASE+1 ;transmit right
jmp LOOP
Figure 6-5 Passthrough Main Loop
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RUNNING THE PASS-THROUGH CODE
Digital Pass-Through
6.2
DIGITAL PASS-THROUGH
To use digital input, perform the following tasks:
1. Apply power to the Evaluation Module as shown in Installation Procedures, Section
1-5.
2. Connect the input and output audio cables.
3. Configure the jumpers as shown in the following table:
Freescale Semiconductor, Inc...
Table 6-1 Digital Input
Input Type
Input Connector
Output
Connector
S6
JP20
Electrical
J3
J8
ELC
1-2
Optical
J4
J8
OPT
1-2
4. Press the reset switch S1.
The following screen appears on the LCD:
SELECT: Ver 2.3
Dgtl
Anlg
S2
S3
S4
S5
Figure 6-6 LCD Pass-through Screen
5. Press switch S2 and select digital input. Pass-through code downloads for
approximately two seconds before audio output is heard.
6-6
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RUNNING THE PASS-THROUGH CODE
Digital Pass-Through Jumper Settings
6.3
DIGITAL PASS-THROUGH JUMPER SETTINGS
The following figure shows the jumper settings when using the optical connector. Notice that
JP20 is in and S6 must be set for the appropriate connector (optical or coax).
U11
JP20
U26
JP24
Sample Rate
JP2
73
36
JP 24 Jumper Settings
1-2
3-4
Freq.
On
On
Off
Off
On
Off
On
Off
32 KHZ
44.1 KHZ
48 KHZ
96 KHZ
DSP
U2
108
109
S6
37
JP4
144
ELC OPT
72
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PLD
1
Figure 6-7 Jumper Settings for Digital Pass-Through
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RUNNING THE PASS-THROUGH CODE
Analog Pass-Through
6.4
ANALOG PASS-THROUGH
To use analog input, perform the following tasks:
1. Apply power to the Evaluation Module as described in 1.4 Installation Procedures.
2. Connect the input and output audio cables.
3. Configure the jumpers as shown in the following table:
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Table 6-2 Analog Input
Input Type
Input Connector
Output
Connector
JP20
Analog
J7 Pins 2 and 3
J8
No Jumper
4. Press RESET switch S1. The following screen appears on the LCD:
SELECT: Ver 2.3
Dgtl
Anlg
S2
S3
S4
S5
Figure 6-8 LCD pass-through Screen
5. Press switch S3 to select analog input. Pass-through code downloads for
approximately two seconds before audio output is heard.
6-8
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RUNNING THE PASS-THROUGH CODE
Analog Pass-Through Jumper Settings
6.5
ANALOG PASS-THROUGH JUMPER SETTINGS
The following figure shows the jumper settings when using analog inputs. Notice that JP20 is
removed and JP24 must be set according to the sampling rate.
U11
JP20
JP24
Sample Rate
Note:
If U26 is populated with
P/N CS8412, the sampling
rate will be 48 KHZ.
JP2
73
36
JP 24 Jumper Settings
1-2
3-4
Freq.
On
On
Off
Off
On
Off
On
Off
32 KHZ
44.1 KHZ
48 KHZ
96 KHZ
DSP
U2
108
109
S6
37
JP4
144
ELC OPT
See Note
U26
72
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PLD
1
Figure 6-9 Jumper Settings for Analog Pass-Through
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RUNNING THE PASS-THROUGH CODE
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Analog Pass-Through Jumper Settings
6-10
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INDEX
Numerics
256FS_CLK, 2-5, 2-12
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A
A/D converter
description, 2-5
reset, 2-6
A/D sampling rate select, 2-5
analog I/O
block diagram, 2-10
clocking, 2-4
connectors, 2-3
description, 2-3
analog pass through, 6-8
jumper settings, 6-9
B
basic features, 1-1
block diagram, 1-1
board
contents, 1-2
BOM, 5-1
C
clock
frame sync, 2-6
serial, 2-6
system, 2-6
clocking
digital I/O, 2-11
connections
cable, 1-6
computer, 1-6
power, 1-6
connectors
analog I/O, 2-3
digital I/O, 2-11
conventions, ix
where to find, 3-1
DAX
description, 2-13
demonstration configuration, 1-4
digital I/O
block diagrams, 2-14
clocking, 2-11
connectors, 2-11
description, 2-11
primary block diagram, 2-14
secondary block diagram, 2-14
documentation, 3-1
DSP
clock source, 2-19
operating mode select, 2-21
DSP clock, 2-15
E
EPROM, 2-28
equations
PLD, 5-6
ESD cautions, 1-5
evaluation platform, 1-2
expansion connector, 2-23
expansion port, 2-23
external memory
block diagram, 2-28
F
features
basic, 1-1
H
hardware
connections, 1-5
description, 1-3
evaluation module, 1-3
user-supplied, 1-3
HC08
reset, 2-20
D
D/A
converter select, 2-19
D/A converter
default settings, 2-7
description, 2-7
reset, 2-9
serial data outputs, 2-9
software mode, 2-7
software mode settings, 2-8
datasheets
MOTOROLA
I
installation
procedure, 1-5
software, 1-6
J
jumpers
as installed, 2-1
default locations, 2-2
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INDEX
software development
hardware, 1-4
software mode settings
D/A converter, 2-8
SRAM, 2-28
suggested reading, ix
M
MC68HC711, 2-8
MC68HC711E20, 2-15
block diagram, 2-15
memory, 2-26
O
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OnCE port, 2-24
direct connection, 2-24
RS-232 interface, 2-25
overview, 1-1
P
pass through code
digital pass through, 6-6
digital pass through jumpers, 6-7
interrupt service routines, 6-1
main loop, 6-5
operation, 6-1
receive input buffer, 6-2
running, 6-1
transmit interrupt service, 6-3
transmit output buffer, 6-3
PLD
clock, 2-17
functions, 2-17
input clocking, 2-4
PLD equations, 5-6
power supply
cautions, 2-29
DSP, 2-30
requirements, 2-29
R
RS-232/MC68HC711
interface, 2-16
S
S/PDIF
receiver, 2-12
transmitter, 2-13
transmitter serial data output, 2-13
schematics, 4-1
SCKR, 2-6
SCKT, 2-6
serial data input, 2-6
setup
options, 2-1
software
demonstration, 1-6
Index-2
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Freescale Semiconductor, Inc.
How to reach us:
USA/Europe/Locations Not Listed:
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
(303) 675-2140
(800) 441-2447
MFAX:
[email protected]
TOUCHTONE (602) 244-6609
US & Canada ONLY
(800) 774-1848
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Tai Po, N.T., Hong Kong
852-26629298
Japan:
Nippon Motorola Ltd.
SPD, Strategic Planning Office
4-32-1, Nishi-Gotanda
Shinagawa-ku, Tokyo, Japan
81-3-5487-8488
Internet:
http://www.motorola-dsp.com
Technical Resource Center:
1 (800) 521-6274
DSP helpline email:
[email protected]
DSP56362EVMUM/AD
Revision 2.5
02/01
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