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Figure 3-9 Programming a Quad Serial Configuration Device with the SFL Solution Note: Before programming the quad serial configuration device, please set the FPGA configuration mode switch (SW6) to ASx4 mode. 3.5 Clock Cir cuits Figure 3-10 is a diagram showing the default frequencies of all of the external clocks going to the Cyclone V SoC FPGA. Figure 3-10 Block diagram of the clock distribution 20
