Download External memory interface for TC1775

AP32035
TC1775 EXTMEM
EBU configuration
Burst length
EIFBLEN (Burst Length)
2
01B = 2 data accesses
4
10B = 4 data accesses
8
11B = 8 data accesses
2
01B = 2 data accesses
4
10B = 4 data accesses
FBBLEN (Buffer Length)
010B = 8 linear burst data cycles
001B = 4 linear burst data cycles
In case of a instruction cache miss each burst access to the external Flash memory
begins at the missed address. The alignment of a cache line results to an 8-word address
line border (address bits A[4:0] = 0).
Application Note
20
V 1.1, 2002-09