Download External memory interface for TC1775

AP32035
TC1775 EXTMEM
Connecting memories to the TC1775 EBU
6.2.1
Configuration
Definitions:
CPU clock: fSYS = 40MHz, tSYS = tCYCLE = 25ns
SRAM write/read timing: tRC = 15ns , tWC = 15ns
Base address = 0xA0000000, SRAMs connected to CS0
SRAM in asynchronous mode, 32-Bit bus width (2 x 16-Bit)
0 read Wait states, 0 write Wait states, 0 hold cycles, 0 recovery cycles
Address range:
4MBit + 4MBit = 8MBit = 1 MByte (256k x 32)
A[26:20] will be compared to EBU_ADDSEL0.BASE
A[19:0] will be used to address memory within 1 Mbyte address range
EBU_BUSCON0.MASK = 0111B, 7 address bits used for address comparison.
// SRAM address range = 0xA0000000 .. 0xA00FFFFF
// setting EBU_BUSCON: Bus configuration register
psEBU = (EBU *)(EBUA_BASE);
// pointer to EBU structure
psEBU->EBU_CON=0x0000FF68;
// Time-Out = 0xFF x 8 clock cycles
// EBU=ext. Master, Ext.Access to FPI Bus
// AGEN=0 -> demultiplexed mode
psEBU->EBU_BUSCON0=0x00020000;
// 32Bit, No Waitstates,
// No hold + recovery cycles
psEBU->EBU_ADDSEL0=0xA0000071;
// Enable region 0, Mask=7,
// Base = 0xA0000000
Note: It is recommended to make the setup of the External Bus Configuration in register
EBU_BUSCONx before the address range will be enabled in register
EBU_ADDSELx
Application Note
28
V 1.1, 2002-09