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Chapter 4. Image Sensor Design
input signal of the lower nand-gate (nand1) goes low. Consequently it changes its state leading to a
high 2 . The upper nand-gate (nand2), however, is switched off as long as 2 is low. Hence, a change
in the signal 1 , which is still high, can only happen when 2 has gone high.
Switching back by pulling az low gives the same behaviour in the opposite direction. The clock
signal 2 can only go low if 1 is already high. For this reason, the case that both clocks are low
at the same time never occurs. The non-inverted clock 1 also required for the amplifier control is
obtained by inverting the 1 signal before passing the last inverter. One clock circuit is used to drive
the complete row of 386 calibration amplifiers. Therefore, the last inverter stages have to drive a high
capacitive load. They are implemented with a medium driver strength (W = 6 m for the PMOS) in
order to achieve slow switching times in the region of 100 ns. This reduces the crosstalk between
clocks and analog signals.
4.2.4 Reference current generation
In order to calibrate one complete pixel row at the same time, not only the calibration amplifier but
also the reference current is required individually for each column. The generation of a number
of equal currents can be achieved by using the corresponding number of transistors and biasing
them with the same voltage. Due to device mismatch, however, the resulting currents differ from
each other. The typical magnitude of the current variations has been measured in the case of large
transistors driven in weak inversion and is presented in section 2.2.2. The current non-uniformities
can be further reduced by applying a special layout implementation: dividing one transistor in several
parts and spreading them over a large area. By this means, higher spatial frequencies of the process
parameter variations are averaged.
Figure 4.13 shows the circuit diagram of one complete current source transistor and parts of the
adjacent ones. They are implemented as NMOS devices, which means, that they actually represent
current sinks. Nevertheless, they are usually called sources if the sign of the current is not important.
The transistor belonging to the n-th column is highlighted. It is composed of five smaller transistors in parallel which are spread over five neighbouring columns. On the other hand, one column
includes five sub-transistors corresponding to the adjacent columns. The absolute current magnitude
is controlled by the bias voltage Vb , which is generated by a current mirror outside the transistor row.
n-2
n-1
Iref
Iref
n
Iref
n+1
Iref
n+2
Iref
Vb
M1n
Mn2
column n-2
column n-1
Mn3
column n
Mn4
column n+1
Mn5
column n+2
Figure 4.13: Circuit diagram of the spread current source transistors to reduce the column-to-column variations. The five parts corresponding to the middle current source (column n) are highlighted.