Download Comparing the NDS and VERA environments for scan chain

Time is modeled by an integer, i.e., time is divided iuto time slots. This suffices for
syuchrouous logic circuits.
Wheu describing combiuatoriallogic, an output port value ouly depeuds on the input port
values, so we can muit time t, and denote the value on a port by 1/( op).
6.2
Internal state of a eell
Since there will be a finite set of memory elemeuts, a cell C will have a finite set of states
iu which it cau beo We cau therefore associate each state with a llluque naturaluumber.
Definition 6.5: [(internal) state of a eell] Let C ELL be a set of cells, and C E C ELL.
The (internal) state of C (deuoted state) is a relatiou on C and the time t defined by
state: C ELL
X
IN
--t
IN
o
Let CELL be a set of cells, CE CELL, aud denote
theu:
state( C, t
+ 1) =
fe( state( C, t), I/(iPl, t), 1/( iP2' t), ... , v(iPIIP(C)I' t))
6.3
Funetionality of a eell
6.3.1
Funetionality of an output port of a eell
In general, the value of au output port, iu time slot t + 1, is a function of the input port
values in time slot t, aud the iuternal state iu time slot t.
Let CELL be a set of cells, CE CELL, aud agaiu deuote
theu:
v( op, t + 1) = fop ( state( C, t), v(iPb t), v(iP2' t), ... , v(iPIIP(C)I' t))
6.3.2
Combinatorial and sequential output ports
Definition 6.6: [eombinatorial] Let CELL be a set ofcells, CE CELL. Combinatorial
(denoted by comb) is a relation on 0 P( C) defined by
comb: 0 P( C)
36
--t
18
© Philips Electrorucs
N.V. 1993