Download MPC107 PCI Bridge/Memory Controller User`s Manual

Freescale Semiconductor, Inc.
Address Map B Options
Freescale Semiconductor, Inc.
Table 3-6. Address Map B—PCI Memory Master View in
Host Mode Options (Continued)
PCI Memory Transaction Address Range
Freescale Semiconductor, Inc...
Hex
Decimal
Local Memory
Address Range
Definition
FD00_0000
FDFF_FFFF
4G - 48M
4G - 32M - 1
0000_0000–00FF_FFFF
Local memory space
(16 Mbytes), 0-based2
FE00_0000
FEFF_FFFF
4G - 32M
4G - 16M - 1
No local memory cycle
Reserved3
1. This address range is separately programmable (see Section 4.9, “Address Map B Options Register—0xE0”)
for the processor interface and the PCI interface to control whether accesses to this address range go to local
memory or PCI memory.
2. If AMBOR[PCI_FD_ALIAS_EN] = 1 (see Section 4.9, “Address Map B Options Register—0xE0”), the MPC107
forwards PCI memory transactions in this range to local memory with the 8 most significant bits cleared (that is,
0x00 || AD[23:0]).
3. The MPC107 will respond to PCI memory cycles in the range PCSRBAR to PCSRBAR + 4 Kbytes (for runtime
registers). PCSRBAR can be programmed to be anywhere from 0x8000_0000 – 0xFCFF_FFFF or from
0xFE00_0000 – 0xFEFF_FFFF.
Figure 3-5 shows the optional PCI compatibility hole and PCI alias space in map B.
.
Processor
View
PCI Memory Space
0
640 KB
1 MB
0
PCI
Compatibility Hole
PCI transactions
in the compatibility
hole are ignored by
the memory controller
Not accessible from PCI
Compatibility Hole
640 KB
1 MB
16 MB
16 MB
TOM
2G
4 GB - 48 MB
PCI alias space
4 GB - 32 MB
PCI transactions
in the alias space
are translated to the
local memory space
4G
4G
Figure 3-5. Address Map B PCI Options in Host Mode
Chapter 3. Address Maps
For More Information On This Product,
Go to: www.freescale.com