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Download MPC107 PCI Bridge/Memory Controller User`s Manual
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Freescale Semiconductor, Inc. SDRAM Interface Operation Freescale Semiconductor, Inc. MDH[0:31] MDL[0:31] PAR[0:7] Memory Data Bus SDMA[13:0] SDBA[1:0] SDRAS To all SDRAM Devices in Common SDCAS WE Freescale Semiconductor, Inc... CKE SDRAM_CLK[0:3] CS[0:7] (optional) CS0 Buffers MPC107 0 1 2 3 4 5 6 7 DQM[0:7] CS1 8Mx8 SDRAM 2Mx8 SDRAM A[11:0] 2Mx8 SDRAM BA[1:0] A[0-11] RAS 2Mx8 SDRAM BA[0-1] A(11-0) CAS RAS 2Mx8 SDRAM BA(1-0) A(11-0) WE DQ[7:0] CAS RAS 2Mx8 SDRAM BA(1-0) A[0-11] CKE WE DQ[0-7] CAS RAS 2Mx8 SDRAM BA[0-1] A[0-11] CLK CKE WE DQ(7-0) CAS RAS 2Mx8 SDRAM BA[0-1] A[0-11] CS CLK CKE WE DQ(7-0) CAS RAS BA[0-1] A[0-11] DQM CS CLK CKE WE DQ[0-7] CAS RAS BA[0-1] DQM CS CLK CKE WE DQ[0-7] CAS RAS DQM CS CLK CKE WE DQ[0-7] CAS DQM CS CLK CKE WE DQ[0-7] DQM CS CLK CKE DQM CS CLK DQM CS DQM MDH[0:7] MDH[8:15] MDH[16:23] MDH[24:31] MDL[0:7] MDL[8:15] MDL[16:23] MDL[24:31] 0 1 2 3 4 5 6 7 8Mx8 SDRAM 2Mx8 SDRAM A[11:0] 2Mx8 SDRAM BA[0:1] A[0-11] RAS 2Mx8 SDRAM BA[0-1] A(11-0) CAS RAS 2Mx8 SDRAM BA(1-0) A(11-0) WE DQ[7:0] CAS RAS 2Mx8 SDRAM BA(1-0) A[0-11] CKE WE DQ[0-7] CAS RAS 2Mx8 SDRAM BA[0-1] A[0-11] CLK CKE WE DQ(7-0) CAS RAS 2Mx8 SDRAM BA[0-1] A[0-11] CS CLK CKE WE DQ(7-0) CAS RAS BA[0-1] A[0-11] DQM CS CLK CKE WE DQ[0-7] CAS RAS BA[0-1] DQM CS CLK CKE WE DQ[0-7] CAS RAS DQM CS CLK CKE WE DQ[0-7] CAS DQM CS CLK CKE WE DQ[0-7] DQM CS CLK CKE DQM CS CLK DQM CS DQM DQM0 DQM1 8Mx8 SDRAM A[11:0] BA[1:0] RAS CAS WE DQ[7:0] CKE CLK CS 0 DQM 8Mx8 SDRAM A[11:0] BA[1:0] RAS CAS WE DQ[7:0] CKE CLK CS 1 DQM PAR[0:7] Bank 0 8M x 72 64 MByte MDH[0:7] MDH[8:15] MDH[16:23] MDH[24:31] MDL[0:7] • • • MDL[8:15] MDL[16:23] MDL[24:31] PAR[0:7] ••• Bank 1 8M x 72 64 MByte Banks 2-7 NOTES: 1. All signals are connected in common (in parallel) except for CS[0:7], SDRAM_CLK[0:3], the DQM signals used for parity, and the data bus. lines 2. Optional parity memories may use any DQM signal. To minimize loading, a different DQM line is recommended for each bank: DQM0 for Bank 0, DQM1 for Bank 1, etc. 3. Each of the CS[0:7] signals correspond with a separate physical bank of memory; CS0 for the first bank, etc. 4. Buffering may be needed if large memory arrays are used. 5. SDRAM_CLK[0:3] signals may be apportioned among all memory devices. Figure 6-3. Example 512-MByte SDRAM Configuration With Parity MPC107 PCIB/MC User’s Manual For More Information On This Product, Go to: www.freescale.com
