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PCI Interface Configuration Registers
4.2.9
Subsystem ID—Offset 0x2E
Table 4-13 describes the subsystem ID register.
Table 4-13. Subsystem ID—0x2E
1
Bits
Reset Value
msb
15–0
x1
Description
Value is determined at startup through configuration pins MDH[0:15] but can be
programmed by software after reset.
Initial value depends on reset configuration signal. See Section 2.4, “Configuration Signals Sampled at Reset.”
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4.2.10 PCI Interrupt Line—Offset 0x3C
Table 4-14 describes the PCI interrupt line register (ILR).
Table 4-14. Interrupt Line Register—0x3C
Bits
Reset Value
Description
msb 7–0
0x00
Contains the interrupt routing information. Software can use this register to hold information
regarding on which input of the system interrupt controller corresponds to the INTA signal.
Values in this register are system-architecture-specific.
4.2.11 PCI General Control Register (PGCR)—Offset 0x44
Table 4-15 describes the bit settings for the PCI general control register.
Table 4-15. PCI General Control Register Bit Definitions—0x44
Bits
Reset
Value
R/W
msb 15–6
All 0s
R
5
0
R/W
Controls ability to retry all incoming PCI read transactions to local memory while the
processor core is writing data to the PCI bus (for example, while internal buffers have
data to be written to the PCI bus).
0 Disables ability to retry all incoming PCI memory read transactions to local memory
while the processor core is writing data to the PCI bus
1 Enables ability to retry all incoming PCI memory read transactions to local memory
while the processor core is writing data to the PCI bus
4
x1
R/W
Controls LOCK support and is software programmable.
0 This bit is cleared by default when the MPC8245 is in host mode. Enables LOCK
support only if the MPC8245 is the target of a locked transaction.
1 This bit is set by default when the MPC8245 is in agent mode. Disables LOCK
support. All locked transactions are treated as non-locked transactions.
3
0
R
4-16
Description
Reserved
Reserved
MPC8245 Integrated Processor User’s Manual
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