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PCI Bus Arbitration
Freescale Semiconductor, Inc...
A configuration signal (MAA2) sampled at the negation of the reset signal (HRST_CTRL)
determines if the on-chip PCI arbiter is enabled (low) or disabled (high). Programming bit
15 of the PCI arbitration control register (PACR) can also enable or disable the on-chip PCI
arbiter. Note that the sense of bit 15 corresponds to the inverse of the polarity of the
configuration signal (that is, when bit 15 = 1 the arbiter is enabled, and when bit 15 = 0 the
arbiter is disabled). See Section 2.4, “Configuration Signals Sampled at Reset,” for more
information about the reset configuration signals.
If the on-chip PCI arbiter is enabled, a request-grant pair of signals is provided for each
external master (REQ[0:4] and GNT[0:4]). Furthermore, an internal request/grant pair for
the internal master state machine of the MPC8245 governs processor accesses to the PCI
and PCI transactions that the DMA controller (functioning as a PCI agent) initiates. If the
on-chip PCI arbiter is disabled, the MPC8245 uses the GNT0 signal as an output to issue
its request to the external arbiter and uses the REQ0 signal as an input to receive its grant
from the external arbiter.
7.2.1
Internal Arbitration for PCI Bus Access
The internal state machine that arbitrates between the two on-chip DMA channels and
processor accesses to the PCI bus is separate from the on-chip PCI bus arbiter that controls
the arbitration between the MPC8245 and external PCI bus masters (enabled by the PCI
arbiter control register at offset 0x46). This internal arbiter for MPC8245 resources is
always enabled, and its output is the combined internal request/grant pair for the MPC8245.
The order of progression of priorities between these accesses is shown in Figure 7-1.
Processor Core-PCI Request/Grant
DMA 0 PCI Request/Grant
DMA 1 PCI Request/Grant
Processor
1
3
2
4
DMA 0
DMA 1
MPC8245
PCI Request/Grant
to PCI Bus Arbiter
Figure 7-1. Internal Processor DMA Arbitration for PCI Bus
As shown in Figure 7-1, the priorities propagate as follows: processor-DMA channel 0processor-DMA channel 1-processor-DMA channel 0, and so on. Processor and DMA
transactions allow for rearbitration (arbiter state transitions) at PCI transaction boundaries.
MOTOROLA
Chapter 7. PCI Bus Interface
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