Download MPC8245UM: MPC8245 Integrated Processor User`s Manual

PCI Bus Arbitration
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configuration register makes more output hold delay values available. Refer to
Section 4.3.2, “Power Management Configuration Register 2 (PMCR2)—Offset 0x72” and
the MPC8245 Integrated Processor Hardware Specifications for more information about
these values and signal timing.
7.1.4
PCI 2.2-Compatible Extensions to MPC8240 and the
Tundra Tsi107™ PowerPC Host Bridge
Freescale Semiconductor, Inc...
The following features are added to the MPC8245 (compared to the MPC8240 and the
Tundra Semiconductor Corporation (Tundra) Tsi107 PowerPC host bridge) for PCI 2.2compatible:
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7.2
The MPC8245 supports the Subsystem ID (2 bytes at offset 0x2E) and Subsystem
Vendor ID (2 bytes at offset 0x2C) registers. Also, the PCI general control register
(2 bytes at offset 0x44) is implemented. Refer to Section 4.2.11, “PCI General
Control Register (PGCR)—Offset 0x44,” for more information.
During the MPC8245 initialization phase, which is extended after hard reset
negates, all incoming PCI transactions to it are ignored. This initialization phase
takes approximately 32 peripheral logic bus clock cycles. Thus, the MPC8245 does
not meet the minimum timing requirement for RST negated to first FRAME
assertion (Trhff) of 5 PCI clocks. See the MPC8245 Integrated Processor Hardware
Specifications, for reset timing requirements.
By default, LOCK is no longer supported when the MPC8245 is configured as an
agent. Thus, the MPC8245 does not sample the LOCK signal in agent mode and
treats all locked transactions as non-locked transactions. For PCI 2.2 compatible,
LOCK should be sampled only when the MPC8245 is in host mode as a target. Note
that a bit in the PCI general control register controls the support of LOCK, and this
bit can be programmed to overwrite this default functionality. Refer to
Section 4.2.11, “PCI General Control Register (PGCR)—Offset 0x44,” for more
information.
PCI Bus Arbitration
PCI bus arbitration is access-based. Bus masters must arbitrate for each access performed
on the bus. The PCI bus uses a central arbitration scheme where each master has its own
unique request (REQ) output and grant (GNT) input signal. A simple request/grant
handshake is used to gain access to the bus. Arbitration for the bus occurs during the
previous access so that no PCI bus cycles are consumed due to arbitration (except when the
bus is idle).
The MPC8245 provides bus arbitration logic for it and up to five other PCI bus masters. The
on-chip PCI arbiter is independent of host or agent mode. The on-chip PCI arbiter functions
in both host and agent modes, or it can be disabled to allow for an external PCI arbiter.
7-4
MPC8245 Integrated Processor User’s Manual
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