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CONTENTS
Paragraph
Number
4.6.1.4
4.6.2
4.6.3
4.7
4.7.1
4.7.2
4.8
4.8.1
4.8.1.1
4.8.1.2
4.8.2
4.8.2.1
4.8.2.2
4.8.2.3
4.8.2.4
4.8.2.5
4.9
4.10
4.10.1
4.10.2
4.10.3
4.10.4
Title
Page
Number
Extended Memory Ending Address Register 1 and 2
—0x98 and 0x9C 4-29
Memory Bank Enable Register—0xA0........................................................
Memory Page Mode Register—0xA3 ..........................................................
Processor Interface Configuration Registers ....................................................
Processor Interface Configuration Register 1—0xA8 ..................................
Processor Interface Configuration Register 2—0xAC .................................
Error Handling Registers ..................................................................................
ECC Single-Bit Error Registers....................................................................
ECC Single-Bit Error Counter Register—0xB8.......................................
ECC Single-Bit Error Trigger Register—0xB9........................................
Error Enabling and Detection Registers .......................................................
Error Enabling Registers 1 and 2—0xC0 and 0xC4.................................
Error Detection Registers 1 and 2—0xC1 and 0xC5................................
Processor Bus Error Status Register—0xC3 ...........................................
PCI Bus Error Status Register—0xC7 .....................................................
Processor/PCI Error Address Register—0xC8 ........................................
Address Map B Options Register—0xE0 .........................................................
Memory Control Configuration Registers ........................................................
Memory Control Configuration Register 1—0xF0 ......................................
Memory Control Configuration Register 2—0xF4 ......................................
Memory Control Configuration Register 3—0xF8 ......................................
Memory Control Configuration Register 4—0xFC......................................
4-30
4-31
4-32
4-32
4-35
4-37
4-37
4-37
4-38
4-39
4-39
4-42
4-44
4-45
4-45
4-46
4-47
4-48
4-51
4-55
4-58
Chapter 5
Processor Bus Interface
5.1
5.1.1
5.1.2
5.1.3
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.3.3.1
5.3.3.1.1
5.3.3.1.2
5.3.3.2
IDT
Tsi107 Processor Bus Configurations................................................................. 5-1
Single-Processor System Configuration ......................................................... 5-1
Dual-Processor System Configuration............................................................ 5-2
Processor Bus Interface Configuration Registers ........................................... 5-3
Processor Bus Protocol Overview ...................................................................... 5-4
Tsi107 Arbitration........................................................................................... 5-5
Address Pipelining and Split-Bus Transactions.............................................. 5-6
Address Tenure Operations ................................................................................ 5-6
Address Arbitration Overview........................................................................ 5-7
Address Tenure Protocol ................................................................................ 5-7
Address Transfer Attribute Signals................................................................. 5-9
Transfer Type Signal Encodings ................................................................ 5-9
Tsi107 Responses to Processor Transactions ......................................... 5-9
PCI-to-Memory Snoop Transactions on 60x Bus................................. 5-11
TBST and TSIZ[0:2] Signals and Size of Transfer .................................. 5-11
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