Download ATX7006 User Manual

The following command sequence can be used to program this pattern into the pattern memory:
CSELECT0
; select module in slot 0, this is the DIO slot.
PB_MEMA0
; set the Pattern Bit memory address counter to 0
PB_MEML0xB,0xB,0x80E,0xC,0xC,0xE,0x7,0xf,0xf,0xf
; load the first 10 pattern words
PB_MEML0xf,0xf,0xf,0xf,0xf, 0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0x40f,0x40f ; load the remaining 15 pattern words
PB_MEM_START0
; set start address to address 0 (red in diagram)
PB_MEM_RET2
; set return to address to address 2 (green in diagram)
PB_MEM_END25
; set end address to address 25 (green in diagram)
CCS0
; select clock source #0 : internal200 MHz clock
CCLKDIV2
; set pre-divider value 2 -> 100MHz clock with 10ns clock width input to pattern
generator
PB_CLKDIV50
; set Pattern clock divider value to 50, to get 500ns pattern steps
4.2.1.5 Serial data IO
Converters with a high speed serial IO interface are getting more common nowadays. The DIO is
equipped with 24 bit shift register, to establish serial communication with these devices. In serial
operation, parallel data bit d0 is used as serial data I/O pin.
The actual number of shift register bits used and shift direction is configurable. This structure is
convenient when a shift register smaller than 24 bits is needed.
For example, in serial input mode, with LSB first (Right-shift data direction), it is not needed to
perform 24 shift actions to align the LSB at the most right position of the shift register. The same goes
for serial output mode with MSB first (Left shift data direction)
The command "DIO_DB" configures the number of shift register stages used. To choose one of the
serial IO modes, use the "DIO_IOMODE" command.
Page 58
ATX7006 user manual rev.2.10