Download iSBC 86/12 Single Board Computer Hardware Reference Manual

iSBC 86/12
Programming Information
Table ;J-20. PIC Operation Procedures (Continued)
Operation
Interrupt Request
Register (IRR)
Status
Procedure
The IRR stores a "1" in the associated bit for each IR input line that is requesting
an interrupt. To read the IRR (refer to footnote):
(1) Write OAH to OOOCO.
(2) Read OOOCO. Status is as follows:
~7 I 06
7
IR Line:
In-Service
Register (ISR)
Status
1
05
5
6
1
04
1
03
4
3
1
02
1
2
01
1
1
00
1
0
The ISR stores a "1" in the associated bit for priority inputs that are being serviced.
The ISR is updated when an EOI command is issued. To read the ISR (refer
to footnote):
(1) Write OBH to OOOCO.
(2) Read DOOCO. Status is as follows:
E·"-I
-06-'"1-0-5 -'--1-04---'1-0-3 -'--1-02---'1--0- 1 -'--1-00--'1
6
7
IR Line:
5
4
3
o
2
Be sure to reset ISR bit at end-of-interrupt when in the following modes:
Auto-Rotating (both types) and Special Mask. To reset ISR in OCW2, write:
~I
06
0
1
I 05 I 04 I 03 I 02 I 01 I 00 I
1
0
0
L1
--...-.L2
LO
-.l
I
BCO identifies bit to be reset.
Interrupt Mask
Register
To set mask bits in OCW1, writl3 the following mask byte to 000C2:
~ 1 06 1 05 1 04
IR Bit Mask:
1 = Mask Set,
o=
M7
M6
M5
Mask Reset
M4
1
03
M3
01
1 02 1
M2
M1
I I
00
MO
To read mask bits, read 000C2.
Special Mask
Mode
The Special Mask Mode enables desired bits that have been previously masked;
lower priority bits are also enabled.
To set, write 68H to DOOCO.
To reset, write 48H to OOOCO.
NOTE:
If previous operation was addressed to same register, it is not necessary to rewrite the OCW.
3-23