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SingMai Electronics 2. PT22 Module description The PT22 aCVi decoder IP core comprises 14 Verilog modules in a hierarchical structure, (see Table 2). aCVi_decoder.v aCVI_ Rx_Register_ control.v aCVi_ Demod.v aCVI_ DemodLPF. v aCVi_ SPG.v aCVi_ data.v aCVi_ Comb_ filter.v Rx_SinCos _ ROM.v Chargen.v aCVi_ Proca mp.v aCVi_ Measure. v Char_Disp_ RAM.v Char_Disp_ ROM.v CG_ROM.v Table 2 PT22 Verilog file structure The top level file is aCVi_decoder.v which, in turn, calls nine of the other modules. aCVi_Demod.v calls a third level file, Rx_SinCos_ROM.v. Chargen.v (the character overlay) call three other modules. PT22 User Manual Revision 0.5 Page 5 of 28
