Download HS-4610

3.18 Watchdog Timer
Once the Enable cycle is active a Refresh cycle is requested before the
time-out period. This restarts counting of the WDT period. When the
time counting goes over the period preset of WDT, it will assume that
the program operation is abnormal. A reset system signal will restart
when such error happens.
The following sample programs show how to enable, disable and
refresh the watchdog timer:
.286
.MODEL SMALL
.DATA
x1
copyright
x2
port
datao
equ
equ
;this is data area
db '------------------------------------------------------',0ah,0dh,'$'
db '|Copyright by Boser technology write by Richard |',0ah,0dh,'$'
db '------------------------------------------------------',0ah,0dh,'$'
04Eh
04Fh
;W83697H Chipset port
;data port
.CODE
print
begin
18
macro
mov
mov
int
endm
proc
mov
mov
STI
buff
dx,offset buff;
ah,09h
21h
near
ax,@data
ds,ax
mov
mov
out
jmp
out
mov
mov
out
jmp
mov
mov
out
jmp
; W83697H
dx,port
; Unlock registor
al,087H
;
dx,al
$+2
dx,al
dx,port
;
al,07H
;
dx,al
$+2
dx,datao ; set device 8
al,08H
;
dx,al
$+2
mov
mov
out
jmp
dx,port
al,030H
dx,al
$+2
; Watchdog IO function
; registor
mov
mov
out
dx,datao
al,01H
dx,al
; set 01h toactivate
;