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Chapter 6
The llc option
-view-legalize-dags
Phase
-view-dag-combine2-dags
Before DAG combine 2
-view-isel-dags
Before instruction selection
-view-sched-dags
After instruction selection and before
scheduling
Before legalization
Fast instruction selection
LLVM also supports an alternative instruction selection implementation called the
fast instruction selection (in the FastISel class, which lives in the <llvm_source>/
lib/CodeGen/SelectionDAG/FastISel.cpp file). The goal of fast instruction
selection is to provide quick code generation at the expense of code quality, which
suits the philosophy of the -O0 optimization level pipeline. The speed gain occurs
by avoiding complicated folding and lowering logic. TableGen descriptions are also
used for simple operations, but more complicated matching of instructions require
target-specific handling code.
The -O0 pipeline also uses a fast but suboptimal register allocator
and scheduler, trading code quality for compilation speed. We will
expose them in the next subsections.
Scheduler
After instruction selection, the SelectionDAG structure has nodes representing
physical instructions—those directly supported by the processor. The next stage
comprises a pre-register allocation scheduler working on SelectionDAG nodes
(SDNodes). There are a few different schedulers to choose from and each one of them
is a subclass of ScheduleDAGSDNodes (see the file <llvm_source>/ lib/CodeGen/
SelectionDAG/ScheduleDAGSDNodes.cpp). The scheduler type can be selected in
the llc tool by using the -pre-RA-sched=<scheduler> option. The possible values
for <scheduler> are the following:
• list-ilp, list-hybrid, source, and list-burr: These options refer to list
scheduling algorithms implemented by the ScheduleDAGRRList class (see
the file <llvm_source>/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.
cpp)
• fast: The ScheduleDAGFast class (in <llvm_source>/lib/CodeGen/
SelectionDAG/ScheduleDAGFast.cpp) implements a suboptimal but
fast scheduler
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