Download HSP50215EVAL User Guide

HSP50215EVAL
JP9 TEST HEADER PIN ASSIGNMENTS
PIN
SIGNAL
DESCRIPTION
PIN
SIGNAL
DESCRIPTION
1
GND
ISA INPUT ADDRESS
2
A
ADDRESS
3
PARA
PARALLEL INPUT ADDRESS
4
A
ADDRESS
5
LIOW
ISA INPUT WRITE
6
WR
WRITE
7
PARWR
PARALLEL INPUT WRITE
8
WR
WRITE
JP10 TEST HEADER PIN ASSIGNMENTS
PIN
SIGNAL
1
SMACLK
2
50Ω - GND
DESCRIPTION
J3 SMA CLOCK INPUT
TERMINATION RESISTOR
JP11 TEST HEADER PIN ASSIGNMENTS
PIN
SIGNAL
DESCRIPTION
1
REGULATED -5.2V
3-21
REGULATED -5.2V SOURCED
FROM ISA BUS INTERFACE
PIN
SIGNAL
2
CARD -VEE
DESCRIPTION
-VEE