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Errata Sheet
Application Hints
It is therefore recommended to update the Transmit Buffer in slave mode after
the transmit interrupt (TIR) has been generated (i.e. after the first SCLK phase).
After reset, the Transmit Buffer may be written at any time.
SSC_TC.H003 Handling of Flag STAT.BSY in Master Mode
In register STAT of the High-Speed Synchronous Serial Interface (SSC), some
flags have been made available that reflect module status information (e.g.
error, busy) closely coupled to internal state transitions. In particular, flag
STAT.BSY will change twice during data transmission: from 0B to 1B at the start,
and from 1B to 0B at the end of a transmission. This requires some special
considerations e.g. when polling for the end of a transmission:
In master mode, when register TB has been written while no transfer was in
progress, flag STAT.BSY is set to 1B after a constant delay of 5 FPI bus clock
cycles. When software is polling STAT.BSY after TB was written, and it finds
that STAT.BSY = 0B, this may have two different meanings: either the transfer
has not yet started, or it is already completed.
Recommendations
In order to poll for the end of an SSC transfer, the following alternative methods
may be used:
•
•
either test flag RSRC.SRR (receive interrupt request flag) instead of
STAT.BSY
or use a software semaphore that is set when TB is written, and which is
cleared e.g. in the SSC receive interrupt service routine.
TC1736, EES-AA, ES-AA, AA
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Rel. 1.2, 26.02.2010