Download Thesis file... - CS 4 - Friedrich-Alexander

1.4
Requirements on the Interrupt Controller
Sloth’s goal is to implement a very concise kernel utilizing hardware components—especially
the interrupt controller. Using hardware for scheduling is supposed to improve the performance
of context switches as compared to software-based schedulers. For this approach, Sloth has
requirements on the interrupt controller of the platform that define whether the system can be
implemented:
• The interrupt subsystem must provide different priority levels for each task and ISR in the
system.
• The interrupt subsystem must support software-generated interrupts, allowing to trigger
individual interrupts in a synchronous manner.
• The platform must provide a way to raise and lower the current execution priority of the
CPU as a synchronization mechanism.
Many modern platforms fulfill these requirements. The reference implementation of Sloth
was achieved on the Infineon TriCore, while this thesis details the implementation on the ARM
Cortex-M3.
1.5
The ARM Cortex-M3
The Sloth concept is not bound to a specific hardware architecture, but can be put into practice
on any platform that fulfills the requirements discussed in Section 1.4. The reference implementation of the Sloth concept was achieved on the Infineon TriCore platform [5], which is commonly
used in the automotive industry. In this thesis, the Sloth design was ported to the ARM
Cortex-M3 microcontroller [6], to see where differences in the hardware design will demand a
different approach in the implementation, which will then be evaluated in the comparison with
the reference implementation in Section 4.2.
1.5.1
Architecture Overview
In 2004, ARM introduced the Cortex-M3 microcontroller, which targets a broad range of embedded system applications especially in the automotive segment [7]. The Cortex-M3 was the first
processor of the ARMv7-M architecture profile, which is meant for small sized embedded systems
optimized for deterministic operation and low-cost applications. The platform is designed as a
32-bit RISC system with a Harvard architecture, on which the processor operates in little endian
byte order for both data and instruction accesses [8, 9].
The Cortex-M3 implements the Thumb-2 instruction set, which consists of mostly 16-bit
instructions with a few additional 32-bit wide instructions. This simultaneous use of instructions
with differing length achieves a higher code density while barely affecting performance. All
instructions are aligned on a halfword boundary. The Thumb-2 instruction set is designed to
support interworking with the older purely 32-bit ARM instruction set, in which all instructions
have to be aligned to word boundary. To allow switching between the two instruction sets at all
branch operations, the current execution mode is being kept as part of the program counter in
bit 0, which is normally not being used due to alignment. On ARMv7-M, this bit must always
be set to ‘1’ to indicate use of the Thumb instruction mode, as only this is supported. This is
4