Download AD7280 Capability Demonstration A Major Qualifying Project

was measured again with a voltage across the system known to corrupt SCLK. The signal obtained is
seen in Figure 65.
Figure 63 – Corrupted SCLK signal
The figure shows that the SDOlo signal has been corrupted by the high voltage and therefore the
entire system data communication becomes corrupted when the voltage rises above 26V across the
system. This also explains the failure of the first test. The first test was done at a voltage of 48V across
the system. Not only is this much higher than the 26V at which the data signals become corrupted, it
would also result in a voltage of about 44V across pins 2 and 3 of the current mirror which is 14V more
across the transistor then the absolute maximum according to the data sheet.
Figure 64 – Healthy SDOlo Signal
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