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Signal Descriptions
assertion of TEA causes the negation/high impedance of DBB in the
next clock cycle. However, data entering the GPR or the cache are
not invalidated.
Negated—Indicates that no bus error was detected.
Timing Comments Assertion—May be asserted while DBB is asserted, and the cycle
after TA during a read operation. TEA should be asserted for one
cycle only.
Negation—TEA must be negated no later than the negation of DBB.
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7.2.9
System Status Signals
Most system status signals are input signals that indicate when exceptions are received,
when checkstop conditions have occurred, and when the MPC603e must be reset. The
MPC603e generates the output signal CKSTP_OUT when it detects a checkstop condition.
For a detailed description of these signals, see Section 8.7, “Interrupt, Checkstop, and Reset
Signals.”
7.2.9.1
Interrupt (INT)—Input
Following are the state meaning and timing comments for the INT input.
State Meaning
Asserted—The MPC603e initiates an interrupt if MSR[EE] is set;
otherwise, the MPC603e ignores the interrupt. To guarantee that the
MPC603e takes the external interrupt, INT must be held asserted
until the MPC603e takes the interrupt.
Negated—Indicates that normal operation should proceed. See
Section 8.7.1, “External Interrupts.”
Timing Comments Assertion—May occur at any time and may be asserted
asynchronously to the input clocks. The INT input is level-sensitive.
Negation—Should not occur until interrupt is taken.
7.2.9.2
System Management Interrupt (SMI)—Input
Following are the state meaning and timing comments for the SMI input.
State Meaning
Asserted—The MPC603e initiates a system management interrupt
exception if MSR[EE] is set; otherwise, the MPC603e ignores the
exception condition. The system must hold SMI asserted until the
exception is taken.
Negated—Indicates that normal operation should proceed. See
Section 8.7.1, “External Interrupts.”
Chapter 7. Signal Descriptions
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