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Timing Considerations
5. In cycle 5, instruction 3 completes, instruction 6 continues through the FPU
pipeline, and although the first stage of the FPU pipeline is free, instruction 7
cannot be dispatched because of the potential need for one of the previous
floating-point instructions to require denormalization. Because instruction 7 cannot
be dispatched neither can instruction 8. This dispatch stall causes the instruction
queue to become full when instructions 10 and 11 are fetched.
6. In cycle 6, instruction 12 is fetched. Instruction 7 is dispatched to the first FPU
stage, so instruction 8 can also be dispatched to the IU. Instructions 9 and 10 move
to IQ0 and IQ1, but because instructions 9, 10, and 11 are integer instructions, only
one instruction is dispatched in each of the next 2 clock cycles. Note that moving
instruction 12 (fadd) up further in the program flow would improve dispatch
throughput.
7. In cycle 7, instruction 6 completes, instruction 7 is in the second FPU execute
stage, and although instruction 8 has executed, it must wait for instruction 7 to
complete. Instruction 9 dispatches to the IU. Instructions 10 and 11 move down in
the IQ. Fetching resumes with instructions 13 and 14.
8. In cycle 8, instruction 7 is in the third FPU execute stage. Instructions 8 and 9 have
executed and they remain in the CQ until instruction 7 completes. Instruction 10 is
dispatched to the IU.
9. In cycle 9, instruction 7 completes, allowing instruction 8 to complete. Because the
CQ is full, instructions 12 and 13 cannot be dispatched.
10. In cycle 10, instructions 9 and 10 complete. Instruction 11 has executed but cannot
exit the CQ from CQ2. Instructions 12 and 13 are dispatched to the FPU and IU,
respectively. Instruction 14 drops into IQ0.
11. In cycle 11, instruction 11 completes and instruction 12 is in the second FPU
execute stage. Instruction 13 has executed but must remain in the CQ until
instruction 12 completes. Instruction 14 enters the first FPU execute stage.
6.3.2.3
Cache Miss
Figure 6-6 shows an instruction fetch that misses the on-chip cache and shows how that
fetch affects the instruction dispatch. Note that a processor/bus clock ratio of 1:2 is used.
The same instruction sequence is used as in Section 6.3.2.2, “Cache Hit.”
A cache miss extends the latency of the fetch stage, so in this example, the fetch stage
represents not only the time the instruction spends in the IQ but also the time required for
the instruction to be loaded from system memory, beginning in clock cycle 3.
Chapter 6. Instruction Timing
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