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Signal Descriptions
Timing Comments Assertion/Negation—The same as A[0:31].
High Impedance—The same as A[0:31].
7.2.5
Address Transfer Termination Signals
The address transfer termination signals are used to indicate either that the address phase
of the transaction has completed successfully or must be repeated, and when it should be
terminated. For detailed information about how these signals interact, see Section 8.3.3,
“Address Transfer Termination.”
7.2.5.1
Address Acknowledge (AACK)—Input
Following are the state meaning and timing comments for the AACK input.
State Meaning
Asserted—Indicates that the address phase of a transaction is
complete. The address bus will go to a high-impedance state on the
next bus clock cycle. The 603e samples ARTRY on the bus clock
cycle following the assertion of AACK.
Negated—(During ABB) indicates that the address bus and transfer
attributes must remain driven.
Timing Comments Assertion—May occur as early as the bus clock cycle after TS is
asserted (unless 603e is configured for 1:1 or 1.5:1 clock modes,
when AACK can be asserted no sooner than the second cycle
following the assertion of TS—one address wait state); assertion can
be delayed to allow adequate address access time for slow devices.
For example, if an implementation supports slow snooping devices,
an external arbiter can postpone the assertion of AACK.
Negation—Must occur one bus clock cycle after the assertion of
AACK.
7.2.5.2
Address Retry (ARTRY)
The ARTRY signal is both an input and output signal on the 603e.
7.2.5.2.1
Address Retry (ARTRY)—Output
Following are the state meaning and timing comments for the ARTRY output.
State Meaning
Asserted—Indicates that the 603e detects a condition in which a
snooped address tenure must be retried. If the 603e needs to update
memory as a result of the snoop that caused the retry, the 603e asserts
BR the second cycle after AACK if ARTRY is asserted.
High Impedance—Indicates that the 603e does not need the snooped
address tenure to be retried.
Chapter 7. Signal Descriptions
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