Download AN 204: Using ModelSim in a Quartus II Design Flow

AN 204: Using ModelSim in a Quartus II Design Flow
Functional/Behavioral HDL Simulation for VHDL Designs
Table 8 provides step-by-step instructions to perform
functional/behavioral HDL simulation for VHDL designs. The first
column shows the GUI steps, and the second column shows the
command-line entries for a simulation.
Table 8. Functional/Behavioral HDL Simulation for VHDL Designs (Part 1 of 4)
GUI
Command Line
Specify the project simulation directory
1.
Choose Change Directory (File menu).
2.
In the Choose a Directory dialog box,
specify the project simulation directory.
3.
Click OK.
cd <full path to project simulation directory> r
Create a new work library
4.
Choose New > Library (File Menu).
5.
Under Create, select a new library and a
logical mapping to it.
6.
In the Library Name box, type work
(default).
7.
Click OK.
vlib work r
Map the design libraries to the work library
8.
Choose New > Library (File Menu).
9.
Under Create, select a map to an existing
library.
14
■
For LPM functions type:
vmap lpm <path to LPM megafunction
library> r
■
For Altera megafunctions type:
vmap altera_mf <path to Altera
megafunction library> r
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