Download ARM Instruction Set

ARM Instruction Set
Privileged mode
In privileged modes the instructions behave as follows:
MSR
MSR
MSR
MRS
MSR
MSR
MSR
MRS
4.5
CPSR_fc, op2
CPSR_f, op2
CPSR_c, op2
Rd, CPSR
SPSR_fc, Rm
SPSR_f, Rm
SPSR_c, Rm
Rd, SPSR
;
;
;
;
;
;
;
;
CPSR{N,Z,C,V,I,F,M[4:0]} <- op2
CPSR{N,Z,C,V} <- op2
CPSR{I,F,M[4.0]} <- op2
Rd <- CPSR{N,Z,C,V,I,F,M[4:0]}
SPSR_mode{N,Z,C,V,I,F,M[4:0]} <- op2
SPSR_mode{N,Z,C,V} <- op2
SPSR_mode{I,F,M[4.0]} <- op2
Rd <- SPSR_mode{N,Z,C,V,I,F,M[4:0]}
Unsigned Word/Byte Data Transfer—LDR and STR
LDR
Load register from memory location.
STR
Store register to memory location.
These instructions come in two forms:
pre-indexed
The syntax of pre-indexed instructions is:
opcode{condition}{B} register,[base{,index}]{!}
post-indexed
The syntax of post-indexed instructions is:
opcode{condition}{B}{T} register,[base]{,index}
where:
B
specifies a byte instead of a word transfer (8 bits instead of 32)
T
is only allowed with a post-indexed load, and forces the transfer to take place
as if in a non-privileged mode (from supervisor mode, for example)
register
is the destination of the load or source of the store
base
must be a register
index
specifies an offset from the base (see below)
For pre-indexed addressing, index is added to base to yield the load or store address. With
post-indexed addressing, base gives the address for the load or store, and base+index is the
value written back to base. In the pre-indexe case, ! enables writeback of base+index to base.
Index
index may be one of the following:
#{–}12-bit-constant-expression
{–}register {, shift #5-bit-constant-expression}
shift is explained in ➲4.3 Data Processing Instructions on page 4-8. In this second form the
value of index is the value in register shifted as specified.
4-12
Reference Manual
ARM DUI 0020D