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Code Listing
library ieee;
use ieee.std_logic_1164.all;
entity demultiplexer is
port(I : in std_logic;
s : in std_logic_vector(0 to 2);
O : out std_logic_vector(0 to 7));
end demultiplexer;
architecture data of demultiplexer is
begin
O(0) <=
O(1) <=
O(2) <=
O(3) <=
O(4) <=
O(5) <=
O(6) <=
O(7) <=
end data;
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(I
(I
(I
(I
(I
(I
(I
(I
and
and
and
and
and
and
and
and
not s(0)
s(0) and
not s(0)
s(0) and
not s(0)
s(0) and
not s(0)
s(0) and
and not s(1) and not s(2));
not s(1) and not s(2));
and s(1) and not s(2));
s(1) and not s(2));
and not s(1) and s(2));
not s(1) and s(2));
and s(1) and s(2));
s(1) and s(2));
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