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Chapter 3 – Hardware Description
3.3
PCI Express Architecture
The PCI Express (PCIe) structure is shown below. All PCIe links operate at Gen1 speeds. The CPU-111-10 does
not support XMC based root complexes, only end-points.
Intel 5100
MCH
PE0 - x8 PCIe
XMC
J15
PE1 - x8 PCIe
XMC
J25
PE2 - x8 PCIe
PLX
PEX8624
PCIe
Switch
ESI
Bus
Intel ICH9R
IOH
PE3 – x4 PCIe
IDT
Tsi384
PE4 – x4 PCIe
IDT
Tsi384
PE5 - x8 PCIe
Intel
82599
PE6 – x4 PCIe
Intel
82571
PE7 – x1 PCIe
Silicon Motion
SM750 VGA
Figure 2: PCI Express Structure
The MCH provides 24 lanes of Gen1 PCIe and acts as the root complex. This is divided into three x8 ports. Two x8
ports connect to the XMC sites. The third x8 port connects to a PLX PEX8624 24-port Switch. This switch "fans
out" the MCH PCIe further as two x4 PCIe links to two IDT Tsi384 PCIe to PCI-X Bridges, providing a PCI-X
interface for each PMC site. The switch also supports a x8 link to an Intel 82599 Dual 10Gb Ethernet Controller,
providing a high-speed connection in the on-board 10GB Ethernet switch fabric.
The ICH9R has two PCIe ports. One x4 port is connected to an Intel 82571 Dual 1Gb Ethernet Controller to
support 1000BASE-T backplane control plane I/O. The remaining x1 PCIe port connects to a Silicon Motion
SM750 Graphics Controller.
3.3.1
Dual XMC Sites
Each XMC Site can support a x8 Gen1 PCIe endpoint per VITA42.3 using connectors J15 and J25. XMC based
root complexes are not supported on the CPU-111-10.
3.3.2
PLX PEX8624 PCIe Switch
The PEX8624 is a 6-port, 24-lane PCI Express switch configured as four ports. It has integrated low power SerDes
on all lanes and supports a fully non-blocking switch architecture. Its cut-thru packet latency is less than 160nSec
between symmetric ports (x8 and x8). The maximum data payload size is 2048 bytes.
Dynatem
CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual
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