Download MSC8102ADS - Freescale Semiconductor

User’s Manual
MSC8102UM/D
Version 1.2
December 17, 2002
MSC8102ADS
User’s Manual
© Motorola, Inc., 2002
Important Notice to Users
While every effort has been made to ensure the accuracy of all information in
this document, Motorola assumes no liability to any party for any loss or
damage caused by errors or omissions or by statements of any kind in this
document, its updates, supplements, or special editions, whether such errors are
omissions or statements resulting from negligence, accident, or any other cause.
Motorola further assumes no liability arising out of the application or use of any
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or consequential damages arising from the use of this document. Motorola
disclaims all warranties regarding the information contained herein, whether
expressed, implied, or statutory, including implied warranties of
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representation that the interconnection of products in the manner described
herein will not infringe on existing or future patent rights, nor do the
descriptions contained herein imply the granting or license to make, use or sell
equipment constructed in accordance with this description.
Trademarks
This document includes these trademarks:
Motorola and the Motorola logo are registered trademarks
of Motorola, Inc.
Windows is a registered trademark of Microsoft Corporation in the U.S.
and other countries.
Intel is a registered trademark of Intel Corporation.
Motorola, Inc., is an Equal Opportunity / Affirmative Action Employer.
For an electronic copy of this book, visit Motorola’s web site at http://e-www.motorola.com/
© Motorola, Inc., 2002; All Rights Reserved
Table of Contents
Section 1 Getting Started
1.1
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.1
JP1 - External Power for CODEC . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.2
JP2,JP3 - EE0,EE1 for Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.3
JP4 - Slave ClockOut Test Point . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.4
JP5 - External Clock Enable for MSC8102 TDM port . . . . . . . . . 18
1.2.5
JP6 - CT-Bus Master Reset Enable . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2.6
JP7 - ADS PON Reset Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Section 2 General Information
2.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5
ADS Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Section 3 Configuration and Installation
3.1
Hardware Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.2
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.2.1
JP1 - External Power for CODEC. . . . . . . . . . . . . . . . . . . . . . . 29
3.1.2.2
JP2,JP3 - EE0,EE1 for Slave. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.2.3
JP4 - Slave Clock Input Source. . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.2.4
JP5 - External Clock Enable for MSC8102 TDM port . . . . . . . 30
3.1.2.5
JP6 - CT-Bus Master Reset Enable . . . . . . . . . . . . . . . . . . . . . . 31
3.1.2.6
JP7 - ADS PON Reset Enable. . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.2.7
JS1-3 - Current Consumption Measurement. . . . . . . . . . . . . . . 31
3.1.2.8
JG1-5 GND Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.2.9
TP13 - Slave Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.3
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.3.1
LD1 - Slave in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.3.2
LD2 - CODEC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.3.3
LD3 - Slave is running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.3.4
LD4 - Host is running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.3.5
LD5 - RS232-1 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.3.6
LD6, LD7 - Host Signaling LEDs. . . . . . . . . . . . . . . . . . . . . . . 33
MSC8102ADSUM/D Ver. 1.2
User’s Manual
III
Table of Contents
3.1.3.7
LD8 - RS232-2 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.3.8
LD9, LD10 - Slave Signaling LEDs . . . . . . . . . . . . . . . . . . . . . 33
3.1.3.9
LD11 - External Power Indicator . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.3.10
LD12 - 3.3V Power Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.3.11
LD13, LD14 - Ethernet Indications. . . . . . . . . . . . . . . . . . . . . . 33
3.1.3.12
LD15, LD16 - 1.5V Power Indicator . . . . . . . . . . . . . . . . . . . . 33
3.2.1
Debug Connection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.2
Standalone Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3
Connecting the ADS Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Section 4 Functional Description
4.1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
Reset & Reset - Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Host Power-On-Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . 42
Slave Power-On-Reset Configuration . . . . . . . . . . . . . . . . . . . . . . 42
Hard/Soft Reset Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Hard Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Host Hard Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Slave Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3
4.3.1
4.3.2
Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Host Main Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Slave Main Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4
60-x Bus Buffering and Muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5
Chip Select Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.6
Local Interrupter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6.1
Host-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6.2
ABORT Interrupt to MSC8101 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6.3
Slave Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6.4
ATM SONET Framer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6.5
Flash Ready Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6.6
Slave-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6.7
ABORT Interrupt to MSC8102 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6.8
TSI Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6.9
FALC56 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6.10
Flash Ready Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.7
IV
SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Table of Contents
4.7.1
4.7.2
SDRAM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.8
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.9
4.9.1
4.9.2
4.9.3
TDM Port Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Time Slot Interchanger (TSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
E1/T1 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.10
RS232 Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.11 Packet Peripherals (Host-side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.11.1
ATM SONET Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.11.2
10/100 T-Base Ethernet Phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.12 Board Control & Status Register - BCSR . . . . . . . . . . . . . . . . . . . 62
4.12.1
BCSR0 - Board Control / Status Register 0. . . . . . . . . . . . . . . . . . 63
4.12.2
BCSR1 - Board Control / Status Register 1. . . . . . . . . . . . . . . . . . 64
4.12.3
BCSR2 - Board Control / Status Register 2. . . . . . . . . . . . . . . . . . 65
4.12.4
BCSR3 - Board Control / Status Register 3. . . . . . . . . . . . . . . . . . 66
4.12.5
BCSR4 - Board Status Register - 4 . . . . . . . . . . . . . . . . . . . . . . . . 67
4.12.6
BCSR5 - Board Identification Register - 5 . . . . . . . . . . . . . . . . . . 68
4.12.7
BCSR6 - Board Miscellaneous Register - 6. . . . . . . . . . . . . . . . . . 69
Section 5 Support Info
5.1
5.1.1
5.1.2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Host 60-x Bus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Slave System Bus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2
Host Memory Controller Registers’ Programming. . . . . . . . . . . . 76
5.3
Slave Memory Controller Registers’ Programming . . . . . . . . . . . 79
5.4
5.4.1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
P1,P5 - Stereo Phone Jack Connectors . . . . . . . . . . . . . . . . . . . . . 84
P2 - SMB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Logic Analyzer Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
P6 - RJ45 E1/T1 Line Connector. . . . . . . . . . . . . . . . . . . . . . . . . . 85
P10 - Slave UART Port Connector . . . . . . . . . . . . . . . . . . . . . . . . 85
P13 - Altera’s In System Programming (ISP) . . . . . . . . . . . . . . . . 86
P14 - Host Debug OnCE (SYS) Connector . . . . . . . . . . . . . . . . . 86
MSC8102ADSUM/D Ver. 1.2
User’s Manual
V
Table of Contents
5.5.8
5.5.9
5.5.10
5.5.11
5.5.12
P15 - Slave Debug OnCE (SLV) Connector . . . . . . . . . . . . . . . . . 88
P17 - EE1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
P20 - Ethernet Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
P23 Power Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
J1 to J5 cPCI Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.6
Program Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.7
Schematics Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
VI
MSC8102ADSUM/D Ver. 1.2
User’s Manual
List of Tables
1-1
2-1
3-1
3-2
4-1
4-2
4-3
4-4
4-6
4-5
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-19
4-18
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
The ADS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
MSC8102ADS Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
The ADS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
The ADS Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Effect of Host (MSC8101) Pins on the Power-on-Reset Configuration. . . . . . . . . . . .43
MSC8101 Hard Reset Configuration Word (HCW1). . . . . . . . . . . . . . . . . . . . . . . . . .44
MSC8102 Pins Dependant upon Power-on-Reset Configuration . . . . . . . . . . . . . . . .46
MSC8102 Hard Reset Configuration Word (HCW2). . . . . . . . . . . . . . . . . . . . . . . . . .47
Slave Memory Controller Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Host Memory Controller Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
SDRAM Mode Register Programming up to 100 MHz . . . . . . . . . . . . . . . . . . . . . . . .56
CODEC Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
BCSR0 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
BCSR1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
BCSR2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
ADS BCSR3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Summary Slave Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
BCSR4 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
BCSR5 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ADS Configuration Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ADS Revision Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
BCSR6 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
BCSR Revision Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Host MSC8101 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Slave MSC8102 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Host’s Memory Controller Initialization for 100(66) MHz . . . . . . . . . . . . . . . . . . . . .76
MAMR Programming (CS4:DSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
MBMR Programming (CS5:ATM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Slave’s Memory Controller Initialization for 100(66) MHz . . . . . . . . . . . . . . . . . . . .79
MAMR Programming (CS3:TSI & CS4:E1/T1 FALC). . . . . . . . . . . . . . . . . . . . . . . .80
MCMR Programming (CS9:L1s & L2 Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
P1,P5 - Stereo Phone Connectors Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . .84
P6 - E1/T1 Line Connector Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5-11
5-12
5-13
5-14
P10 Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
P13 - ISP Connector - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
P14 - Main ONCE Connector - Interconnect Signals. . . . . . . . . . . . . . . . . . . . . . . . . .87
P15 - Slave ONCE Connector - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . .88
MSC8102ADSUM/D Ver. 1.2
User’s Manual
VII
List of Tables
5-15
5-16
5-17
5-18
5-19
5-20
VIII
P17 - EE1 Chain Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
P20 - Ethernet Port Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
J1 - 60x Bus System Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
J2 - 60x Bus System Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
J4 - H.110 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
J5 - MSC8102 Signal Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
MSC8102ADSUM/D Ver. 1.2
User’s Manual
List of Figures
1-1
1-2
1-3
1-4
1-5
1-6
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
5-2
5-3
5-4
5-5
5-6
JP1 - CODEC Power Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
JP2,JP3 - EE0s,EE1s control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
JP4 - MSC8102 ClockOut TP13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
JP5 - TDM External Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
JP6 - CT-Bus Master Reset Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
JP7 - ADS PON Reset Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MSC8102ADS Top-side Part Location Diagram . . . . . . . . . . . . . . . . 26
JP1 - CODEC Power Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
JP2,JP3 - EE0s,EE1s control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
JP4 - MSC8102 Clock Source Select . . . . . . . . . . . . . . . . . . . . . . . . . 30
JP5 - TDM External Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
JP6 - CT-Bus Master Reset Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
JP7 - ADS PON Reset Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TP13 - MSC8102 ClockOut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Host System Debug Scheme A (spitted). . . . . . . . . . . . . . . . . . . . . . . 35
Host System Debug Scheme B (daisy-chained) . . . . . . . . . . . . . . . . . 35
Host System Debug Scheme C (daisy-chained) . . . . . . . . . . . . . . . . . 36
JTAG-Chain on Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Standalone Configuration (ADS board) . . . . . . . . . . . . . . . . . . . . . . . 37
Standalone Configuration (ADSs board) . . . . . . . . . . . . . . . . . . . . . . 37
Ext Power Supply Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power on Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ADS Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Secondary Reset Configuration Details . . . . . . . . . . . . . . . . . . . . . . . 46
Host Clock Distribution Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Slave Clock Distribution Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DSI Bus to 60-x Bus Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Host Interrupt Utilization Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Slave Interrupt Utilization Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SDRAM Slave-side Connection Diagram . . . . . . . . . . . . . . . . . . . . . 56
TDM Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
TDM Clocking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Host RS232 Serial Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Slave UART Serial Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ADS Power Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
P14 connector front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
P15 connector top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
cPCI J1,J4 connectors view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
cPCI J2,J5 connectors view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Schematics. Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
MSC8102ADSUM/D Ver. 1.2
User’s Manual
XI
List of Figures
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
XII
Schematics. Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Schematics. Page 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Schematics. Page 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Schematics. Page 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Schematics. Page 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Schematics. Page 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Schematics. Page 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Schematics. Page 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Schematics. Page 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Schematics. Page 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Schematics. Page 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Schematics. Page 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Schematics. Page 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Schematics. Page 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Getting Started
Section 1 Getting Started
This Quick Start Guide shows MSC8102ADS board switches and jumpers in their default positions.
1.1 Switches
ADS Dual-In-Line Package (DIP) Switches are listed and described in Table 1-1. The switches
and jumpers featured in this chapter are shown with their factory-default positions. ADS board
LED’s are also detailed.
Table 1-1 The ADS Switches
Designator & Purpose
Type
Description
SW4.1-SW4.2 set the MODCK1,2 of MSC8102
Slave to the PLL mode. When “ON”, the value is
zero. When there is a clock-in frequency of
41.6MHz, the clock mode is set to 11.
2 3
MODCK1
4
SYS
ON
1
SW4
Slave Configuration Control
(MSC8102)
MODCK2
DBG
DSI
CFG-S Ctrl
SW4.3 (SYS <-> DSI) selects the power-up
configuration source. MSC8101 Host is the
configuration source when the DSI position is
chosen. If SYS is selected then the MSC8102
Slave Flash is the configuration source.
SW4.4 While in DBG position, EE0 input is high at
the time of Core reset. This allows the Cores to
enter Debug mode immediately after negation of
HRESETs. When not in the DBG position then,
after reset, the Cores run freely. The Debug mode
may be activated by toggling SW4/4.
Factory settings:
- MODCK1,2 are OFF
- Config source from DSI
- Debug mode after Slave’s Hard Reset
SW5.1-SW5.3 set Software Option Bits 0-2 for SW
flow control. When “ON”, the value is zero.
ON
1
2 3
-1
4
SW5
Software Option reading by
MSC8101
-0
HEE1
SW Opt
-2
SW5.4 is used for Host EE1 pin control after
Power-On-Reset. When “ON”, the value is zero.
Reset Factory settings:
- All bits set to ON
MSC8102ADSUM/D Ver. 1.2
User’s Manual
15
Getting Started
SW6.1-SW6.6 set the MODCK1-6 of MSC8101
Host to the PLL mode. When “ON”, the value is
zero. When there is a clock-in frequency of 55MHz,
the clock mode is set to 57.
MODCK
ON
1
2 3
-2
4 5
-6
6 7
-4
8
SW6
Host Configuration Control
(MSC8101)
-3
DBG
SW6.7 sets HCW1 source. When “ON” the source
is Host Flash. If “OFF” then the source is a BCSR
programmed value.
-1
-5
FCFG
CFG-H Ctrl
SW6.8 While in DBG position, EE0 input is high at
the time of Core reset. This allows the Core to enter
Debug mode immediately after negation of
HRESETh. When not in the DBG position then,
after reset, the Core runs freely. The Debug mode
may be activated by toggling SW6/8.
Reset Factory settings:
-Clock Mode is 57
-HCW1 originates from BCSR
-Debug Enable after Host Hard Reset
SW7.1-SW7.2 set the JTAG Chain configuration
Bits 1-2.
ChSel: 1
2
“ON” “ON” - Separate JTAG Access
“OFF” “ON” - Short JTAG Chain
“OFF” “OFF” - Long JTAG Chain
ON
1
2 3
ChSel2
SYS64
4
SW7
JTAG Chain Setting
ChSel1
JTAG_CHAIN
SW7.3 sets the Slave’s System Bus width. When
“ON” the System Data Bus of the MSC8102 is 64bit and the DSI bus is 32-bit. If “OFF” then the
System Bus is 32-bit and the DSI bus is 64-bit.
SW7.4 Reserved.
Reset Factory settings:
-Short JTAG Chain
-MSC8102 System Bus 64-bit
The “JTAG Command Converter” plugs into the
front of connector P14.
SW8
Power Switch
Front
panel
ON
OFF
PCB
SW8
When in the “ON” position power comes from an
external 12V Power Supply via a P23 connector.
When “OFF” the external power supply via P23 is
disconnected. Consequently, when located in the
CPCI backplane, the ADS is then powered by an
internal power supply via cPCI connectors.
1.2 Jumpers
MSC8102ADS jumpers will be noted in the following sub-sections:
16
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Getting Started
1.2.1 JP1 - External Power for CODEC
JP1 selects the source for the CODEC Power Rail. When a jumper is located between pins 1 - 2
of JP1 (Factory Set) then the CODEC feeds from the 3.3V plane of the ADS.
When a jumper is removed the 3.3V @ 200 mA external low-noise power supply may be connected
to JP1 pins 2-3 as illustrated below in Figure 1-1
1
JP1
1
GND
NORM
JP1
GND
NORM
3.3V
3.3V
Factory Set
JP1: 1-2 Close
+3.3V GND
External Power Supply
Figure 1-1 JP1 - CODEC Power Selection
1.2.2 JP2,JP3 - EE0,EE1 for Slave
JP2 and JP3 may be used for debugging purposes - to measure/set MSC8102 signal logic levels.l
JP2
JP3
1
1
EE0
EE1
Factory Set
JP2,3 Open
Figure 1-2 JP2,JP3 - EE0s,EE1s control
1.2.3 JP4 - Slave ClockOut Test Point
Using a scope, JP4 may be utilized for measuring a MSC8102 System Bus Clock.
CLKOUT
Figure 1-3 JP4 - MSC8102 ClockOut TP13
MSC8102ADSUM/D Ver. 1.2
User’s Manual
17
Getting Started
1.2.4 JP5 - External Clock Enable for MSC8102 TDM port
JP5 is used for MSC8102 TDM port test purposes. In the instance that jumper JP5 is closed, the
TDM lines connect to the TSI & E1/T1 Framer devices and from there to expansion connector J5.
If jumper JP5 is open then all TDM signals become available on J5 and, as a consequence, are
isolated from other ADS sections..
1
JP5
CLK MST
Factory Set
JP5 Close
Figure 1-4 JP5 - TDM External Clock Enable
1.2.5 JP6 - CT-Bus Master Reset Enable
If the JP6 is closed then the MSC8102 applies Master Reset for the CT-bus (H.110)..
1
JP6
CTRST
Factory Set
JP6 Open
Figure 1-5 JP6 - CT-Bus Master Reset Enable
1.2.6 JP7 - ADS PON Reset Enable
If JP7 is closed then the ADS exists in a Power-On-Reset state that is used solely for debugging
purposes..
JP7
1
PRST
Factory Set
JP7 Open
Figure 1-6 JP7 - ADS PON Reset Enable
18
MSC8102ADSUM/D Ver. 1.2
User’s Manual
General Information
Section 2 General Information
2.1 Introduction
This user guide describes the engineering specifications of the MSC8102ADS board. The
board is based on the MSC8102 - a highly integrated system-on-a-chip device containing four
StarCore SC140 DSP Cores. The System Interface Unit (SIU) for the MSC8102 is similar to that
of the MSC8101.
The board is intended to serve as a platform for software (s/w) and hardware (h/w) development
in the MSC8102 processor environment. On-board resources and the associated debugger enable
developers to perform a variety of tasks: download and run code; set breakpoints; display memory
and registers; and, connect proprietary h/w via the expansion connectors. The MSC8102 processor enables the incorporation of these features into selected systems.
The ADS may be used as a demonstration tool. For example, application s/w may be burnedA
into the ADS’ flash memory and run in exhibitions. ADS boards are produced with two configurations - the “Complete” configuration provides host processor features while the “Single” configuration is used solely for evaluating the MSC8102.
2.2 List of Abbreviations
•
•
•
•
•
•
•
•
•
•
•
•
•
ADS - MSC8102ADS, the document subject
BCSR - Board Control & Status Register
CPM - Communication Processor Module
CW - Metrowerks CodeWarrior IDE for StarCore
DIP - Dual-In-Line Package
DMA - Direct Memory Access
DSI - Direct Slave Interface
GPCM - Memory Controller General Purpose Chip-select Machine
GPL - General Purpose Line (associated with a UPM)
HCW - Hardware Configuration Word
SDRAM Machine - Memory Controller Synchronous Dynamic RAM Machine
UPM - Memory Controller User Programmable Machine
ZD - Clock Zero Delay Buffer with internal PLL for skew elimination
2.3 Related Documentation
[1] MSC8102 - MSC8102 Specification
[2] MSC8101 Data Sheet
[3] SWITI Switching Device PEF24471 HTSI-XL. Wired Communication. Data
Sheet.
A. Either on-board or off-board.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
19
General Information
2.4 Board Specifications
Specifications for the MSC8102ADS are provided below in Table
2-1.
Table 2-1 MSC8102ADS Specifications
CHARACTERISTICS
SPECIFICATIONS
Power requirements
9-18V external DC power supply.
For 12V max current 1.2A
MSC8101/MSC8102 multicore (4xSC140 core) DSP
Internal clock runs up to 300MHz @ 1.6V
MSC8101 (Host-side) 60x Bus (DSI)
MSC8102 (Slave-side) System Bus
System and 60x Buses both running up to 100 MHz Clock
Frequency.
MSC8101:
PowerPC (60x) bus:
4GB (32 address lines) @ 64bit Data
Local Bus:
Addressing:
External Decoding: 16MB (24 address lines)
Internal Decoding: 4GB (32 address lines)
Data Bus Width:
MSC8102 DSI bus (non-buffered).
SDRAM 100MHz soldered (non-buffered)
Flash memory (buffered)
BCSR (buffered)
AMT Framer (buffered)
MSC8102 System Bus:
Addressing:
64-bit
2MB organized as 32-bit (default conf.) or 64-bit.
16MB,organized on two devices 4Bank x 4Meg x 32-bit.
4MB, 16-bits wide.
BCSR contains eight byte-size registers.
1KB, 8-bits wide.
64/32 -bit - dependant upon the configuration mode
4GB (32 address lines)
SDRAM 100MHz soldered (non-buffered).
64-bit configuration
32-bit configuration
Flash memory (buffered)
16MB on two devices 4Bank x 4Meg x 32-bit
8MB on a single device 4Bank x 4Meg x 32-bit
4MB organized 4Meg x 8-bit
Operating temperature
0OC - 30OC (room temperature)
Storage temperature
-25OC to 85OC
Relative humidity
5% to 90% (non-condensing)
Dimensions require 6U CompactPCI® form factor with:
Length
Width
Thickness
233.35 mm
160.0 mm
1.8
mm
2.5 ADS Features
• The ADS is based on the 64-bit MSC8102. Both the System and Direct Slave
Interface (DSI) buses run up to 100MHz.
20
MSC8102ADSUM/D Ver. 1.2
User’s Manual
General Information
• Note that the Host controller MSC8101 and 60-x bus interface with Slave
MSC8102 and its DSI bus.
• ADS Configurations:
o
MSC8102ADS: “Complete” configuration includes a host controller.
o
MSC8102ADSs: “Single” configuration is without both host controller and peripherals. Only the MSC8102 is populated.
• The MSC8102 Interface:
o
DSI bus is a slave of the MSC8101 with its 60-x bus.
o
DSI may be configured to 32-bit when the System bus is sized at 64-bit (default
mode) or visa versa (DSI 64-bit/System bus 32-bit).
o
The Memory Controller Synchronous Dynamic RAM (SDRAM) Machine controls
either 8 or 16MB of SDRAM memory size on the System bus. The size of memory
is dependant upon the System’s bus configuration.
o
Features a 4MB @ 8-bit size Flash for configuration/boot/program storage.
o
Four MSC8102 TDM ports are connected to the Infineon TSI PEF24471 device.
The device allows the interconnecting of T1/E1 time-slots between the Infineon
FALC PEB2256 and the Dual CODEC MT92303. An interface with the H.110
TDM bus on the J4 Compact PCI connector is also available.
o
RS232 Transceiver MAX3241 supports the UART port operation of the MSC8102.
• The MSC8101 Interface:
o
Acts as a host for the MSC8102.
o
SDRAM machine controls 16MB SDRAM on 60-x bus.
o
Features a 4MB @16-bit size Flash for configuration/boot/program storage.
o
Communication Processor Module (CPM) ports are connected to the following:
ATM Framer PM5384 with Optical I/F (FCC1); 10/100 Base-T Phy L80225 of LSI
Logic (FCC2); RS232 Transceiver MAX3241(SCC1).
o
An 8-bit Board Control & Status Register (BCSR) is required for MSC8102ADSc
configuration.
• Board Capabilities:
o
Programmable Hard Reset Configuration for MSC8102 is executed from the Flash
memory or the DSI bus. This configuration type may also be forced from the BCSR.
o
Boot for the MSC8102 is available from the Host controller via the DSI bus and
from the System bus (Flash). Boot may also be performed from the UART or TDM
ports.
o
To facilitate the measuring of MSC8102 signals, high density (MICTOR) Logic Analyzer connectors are used.
o
When used as expansion connectors, CompactPCI® connectors J1,J2 and J5 carry MSC8102 signals to off-board tools thus enabling chip verification and evaluation.
o
Debugging is performed via an external Command Converter that is connected eiMSC8102ADSUM/D Ver. 1.2
User’s Manual
21
General Information
ther to both of the OnCE 14-pin headers or, alternatively, to one or the other of
them. There is one OnCE 14-pin header for each processor.
22
o
The OnCE debug chain allows, via backplane, the connection of additional ADS
boards.
o
After reset the Debug Enable/Disable and Debug Request options may be selected. The processor’s EE pins enable and support the noted options.
o
Board Identification and board status may be read via the BCSR.
o
An SMB form RF-connector enables the connection of an external pulse generator
to the clock input of the MSC8102.
o
Variant board configurations are made available via the Dual-In-Line Package
(DIP) Switch setting.
o
The board features push buttons for both the Host and Slave: Power-On Reset;
Soft Reset; Hard Reset; and, ABORT.
o
The board is powered by a single 9 - 18V external DC Supply with on-board reverse polarity protection.
o
Voltage is provided to the board’s DC-DC Converter. The Converter has the following parameters: 3.3V @ 4A 10%.
o
The DC-DC Converter powers two voltage regulators: 1.3 - 1.7V adjustable linear
voltage regulator for the MSC8102; and, the 1.6V linear voltage regulator for the
MSC8101.
o
The Software Option Switch provides 8 s/w options via the BCSR.
o
The LED’s indicate the following: power supply; peripheral enables; EE1-pin status; and, s/w signals.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
General Information
J2
JTAG/OnCE
14pin
JTAG/OnCE
14pin
64
60-x bus
64-bit
ATM
Framer
4Megx16
SDRAM1-1
Reset Config,
Boot Code
HOST-side
1
NMIh
TDM ch.
SLAVE-side
T1/E1
Framer
(FALC)
TDM3
TDM[0-2]
GPIOx2
NMIs
Reset Config,
Boot Code
Board Control
Status
Register
Reset Config,
Boot Mode
B
RESETs
FLASH2
4MB@8bit
2
Configurations:
1 Complete board
MSC8102
3-pin
8
Enable
MAX3241
DB9
RS232-1
PORT
8
CLKOUT
SDRAM2-1 H
4Megx16
8MB@32bit
SDRAM2-2 L
4Megx16
8MB@32bit
16MB@64bit
2 Single board
32H
32L
16
Ext CLK
SYS/DSI
SDRAM1-2
FLASH1
4MB@16bit
A
MSC8102
PEF24471
Time Slot
Interchanger
2048 TS
Reset Config,
Boot Code
RJ45
Network
on socket or
soldered
20MHz
400pins 0.8mm
(Open Top 3M Socket)
DSI
MSC8101
ATM
Optical
UART
10/100
T-Base
Phy
RJ45
JTAG
Ethernet
20MHz
RS232-2
PORT
J1
MAX3241
To
Command
Converter
CPCI Expansion Connectors
T1/E1
ST bus
Dual
CODEC
V.Detector
9-18V DC
3.3V
DC-DC
4A
1.6V
1.6V
To 8101 To 8102
uPort
Expansion Connector J5
* - Additional memory part is optional
H110 TDM Bus
A
J4
Legend:
On-socket Device
BCSR controlled
B - Two parts of single MSC8102
Figure 2-1 System Block Diagram
MSC8102ADSUM/D Ver. 1.2
User’s Manual
23
General Information
24
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Configuration and Installation
Section 3 Configuration and Installation
3.1 Hardware Preparation
This chapter contains installation instructions for the MSC8102ADS board.
CAUTION:
Be sure to switch off or disconnect power when reconfiguring an installed
ADS board. Reconfiguring jumpers with the power on can damage system
circuits.
When you unpack the MSC8102ADS board from its shipping carton, refer to the packing list to
verify that all items are present and in good condition.
NOTE:
If the ADS board arrives damaged, save all packing material and contact
the carrier’s agent.
Parts locations on the ADS board are shows in the Figure 3-1 MSC8102ADS Top-side Part
Location Diagram.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
25
Configuration and Installation
22
20
C2
SW4
37
15
2
10
1
P3
2
place
U7
U10
U11
2
38
DBG
1
SLAVE
SYS2-S
20
1
CTRST
P6
JP5
25 1
1
1
1
1
P7
CLK MST
U9
5
B22
PRPH-S
CLKOUT 8102
SCLOCK
B2
J5
D13
D14
SYS1-S
1
C9
OSC EXT
JP4
JS3
8102 Cnfg
1
D9
P4
P2
LD1
BNKSEL1
1
*
C12
C11
E1/T1
U6
11
EE1
U8
+
1
1
EE0
1
C10
-PLL- JS2
C8
-CORE- JS1
C16
C24
C25
C26
C30
38
DATAL-S
2
38
-0
-1
-2
HEE1
1
-3
-2
-1
-6
-5
-4
FCFG
DBG
SW6
37
144
112 113 60 55
FR4
1
R8
-0
-0
ADDR-H
C44
1
37
T6
T1
A6
A1
U32
3
15
25 1
20
J1
10
U36
1
4
3
5
SW11
1
2
GND
1
RP1
4
SRESET
2
1.5V-s
Adj.
1.5V-h
5
C62
C61
3
1
U34
HOST
System PON
+
PRESET
1
4
SW10
3
HRESET
1
2
PRST
JP7
LD16
C57
D7
D3
C59
+
*
4
P23
C60
*
2
D9
1.5V-s-
U37
L2
L3
HCLOCK
U31
1
+
3
*
SW9 D8
LD15
C56
*
4A
3
2.5V
*
1
-h-
P22
*
2
1
D6
U35
1
SW12
*
SW8
*
D4
+
12VDC
38
ABORT
C55
D2
6
+
2
2
U33
F1
+
C54
D1
1
C58
C52
UTOPIA-8
+
1
+
3.3V
C53
+
C51
+
1
P21
B
D
F
H
K
M
P
15
14
1
ATM
MSC8102ADS
084-00160PROTO
C 2002
TP60
18
C50
17
7
10
5
U27
TP59
1
C47
6
U30
A
C
E
G
J
*
C46
*
C48
5
1
HOST
*
*
LD13 -100MLD14 -FDC49
10
U24
1
*
28
29
C45
38
*
39
U25
2
*
C42
R11
+
U28
CFG
R7
U23
T1
A1
T1
F
E
D
C
B
A
60-x BUS
108
57
REV
U20
A1
109
73
22
C40
C39
T6
72
U21
T6
A6
A6
C38
37
C37
C36
1
37
R10
SW7
DATAL-H
127
126
+
C41
1
8101 place
U26
1
U22
U29
8101 Resets
Figure 3-1 MSC8102ADS Top-side Part Location Diagram
26
J4
2
1
GND
8
R9
ChSel1
ChSel2
SYS64
C43
4
10
10
SW Opt 1 CFG-H Ctrl
U18 36
U17
38
2
JTAG_CHAIN
1
LD12
GND
1
10/100M ETH
H.110
1
ISP/JTAG
C34
C33
C32
P16
RS232-2
U19
-0
*
3.3V
LD11
P20
C35
1
RUN
SIGS SIGH
LD8
LD10
5Vext
P18
RS232-1
*
LD9
37
1
P19
*
-1
LD5
60x,Misc
CODEC
*
*
[H] LD4
LD7
RN4
P13
9
14
2
1
13
LD2
*
2
EE1
Chain
*
*
LD6
RN3
1
1
1
DATAH-H
[S] LD3
1
P12
1
2
OnCE-SLV
OnCE-SYS
P15
37
SW5
1
P11
P17
TP46
TP45
MODCK
37
2
38
1
14
13
P14
JTAG chain
10
8101 Cnfg
TP44
1
B R5
A
17 15
R6
P10
RS232-2
C31
DATAH-S
1
J2
GND
C22
FR3
C29
C28
U14
C21
+
C20
R3 RN2
H R4
G
1
1
C23
C27
P9
2
1
AB22
AB2
U
T
RN1
R
P C18 1
N
M
L
R2
5
5
P8
1
U15
1
C19
1
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
+
C17
R1
10
15
U16
17 15
1
37
C15
38
U12
1
37
ADDR-S
C14
U13
RS232-1
JP6
1
C13
MSC8102ADSUM/D Ver. 1.2
User’s Manual
1
P5
+
+
+
12
44
LINE OUT
1
FR1
+
22
1.5V 3.3V FR2
C7
ARTRY JP2
BNKSEL2
U5
+
34
GND
AACK
3
1
D2 D3
Slave JP3
D8
SW3
21
23 U4
33
C6
SW2
SLAVE
EXCLK
U2
1
C5
+
P1
31
31
SW1
NORM
38
1
1
C4
1
U1
3.3V
1
SYS
+
C3
LINE IN
4
42
ABORT
JP1 61
L1
42
HRESET
GND
SRESET
C1
2
MODCK
-2
-1
DSI
DBG
CFG-S CTRL
F
E
D
C
B
A
8102 Resets
41
U3
Configuration and Installation
3.1.1 Switches
ADS Dual-In-Line Package (DIP) Switches and push buttons are listed and described in Table
3-1 The ADS Switches and Table 3-2 The ADS Push Buttons, respectively. The switches and
jumpers featured in this chapter are shown with their factory-default positions. ADS board LED’s
are also detailed.
Table 3-1 The ADS Switches
Designator & Purpose
Type
Description
SW4.1-SW4.2 set the MODCK1,2 of MSC8102
Slave to the PLL mode. When “ON”, the value is
zero. When there is a clock-in frequency of
41.6MHz, the clock mode is set to 11.
MODCK2
2 3
MODCK1
4
SYS
ON
1
SW4
Slave Configuration Control
(MSC8102)
DBG
DSI
CFG-S Ctrl
SW4.3 (SYS <-> DSI) selects the power-up
configuration source. MSC8101 Host is the
configuration source when the DSI position is
chosen. If SYS is selected then the MSC8102
Slave Flash is the configuration source.
SW4.4 While in DBG position, EE0 input is high at
the time of Core reset. This allows the Cores to
enter Debug mode immediately after negation of
HRESETs. When not in the DBG position then,
after reset, the Cores run freely. The Debug mode
may be activated by toggling SW4/4.
Factory settings:
- MODCK1,2 are OFF
- Config source from DSI
- Debug mode after Slave’s Hard Reset
SW5.1-SW5.3 set Software Option Bits 0-2 for SW
flow control. When “ON”, the value is zero.
ON
1
-0
2 3
-1
4
SW5
Software Option reading by
MSC8101
HEE1
SW Opt
-2
SW5.4 is used for Host EE1 pin control after
Power-On-Reset. When “ON”, the value is zero.
Reset Factory settings:
- All bits set to ON
MSC8102ADSUM/D Ver. 1.2
User’s Manual
27
Configuration and Installation
SW6.1-SW6.6 set the MODCK1-6 of MSC8101
Host to the PLL mode. When “ON”, the value is
zero. When there is a clock-in frequency of 55MHz,
the clock mode is set to 57.
MODCK
ON
1
2 3
-2
4 5
-6
6 7
-4
8
SW6
Host Configuration Control
(MSC8101)
-3
DBG
SW6.7 sets HCW1 source. When “ON” the source
is Host Flash. If “OFF” then the source is a BCSR
programmed value.
-1
-5
FCFG
CFG-H Ctrl
SW6.8 While in DBG position, EE0 input is high at
the time of Core reset. This allows the Core to enter
Debug mode immediately after negation of
HRESETh. When not in the DBG position then,
after reset, the Core runs freely. The Debug mode
may be activated by toggling SW6/8.
Reset Factory settings:
-Clock Mode is 57
-HCW1 originates from BCSR
-Debug Enable after Host Hard Reset
SW7.1-SW7.2 set the JTAG Chain configuration
Bits 1-2.
ChSel: 1
2
“ON” “ON” - Separate JTAG Access
“OFF” “ON” - Short JTAG Chain
“OFF” “OFF” - Long JTAG Chain
ON
1
2 3
ChSel2
SYS64
4
SW7
JTAG Chain Setting
ChSel1
JTAG_CHAIN
SW7.3 sets the Slave’s System Bus width. When
“ON” the System Data Bus of the MSC8102 is
64-bit and the DSI bus is 32-bit. If “OFF” then the
System Bus is 32-bit and the DSI bus is 64-bit.
SW7.4 Reserved.
Reset Factory settings:
-Short JTAG Chain
-MSC8102 System Bus 64-bit
The “JTAG Command Converter” plugs into the
front of connector P14.
SW8
Power Switch
Front
panel
ON
PCB
OFF
SW8
When in the “ON” position power comes from an
external 12V Power Supply via a P23 connector.
When “OFF” the external power supply via P23 is
disconnected. Consequently, when located in the
CPCI backplane, the ADS is then powered by an
internal power supply via cPCI connectors.
Table 3-2 The ADS Push Buttons
SW1
Slave Hard Reset
Pressing button SW1 results in Hard Reset for the
MSC8102 (HRESETh is asserted).
HRESET
28
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Configuration and Installation
SW2
Slave Soft Reset
SRESET
Pressing button SW2 results in Soft Reset for
MSC8102. Despite the reset, clock and chip-select
data as well as SDRAM contents are retained. Soft
Reset causes the Slave’s cores to run free despite
the position of SW4/4.
Pressing and releasing button SW3 results in a
non-maskable interrupt for MSC8102.
SW3
Slave NMI (IRQ0)
ABORT
Pressing button SW9 results in main
Power-On-Reset for both processors, MSC8101
and MSC8102.
SW9
Power-On-Reset (PORESET)
PRESET
Pressing button SW10 results in Hard Reset for
MSC8101. Host Hard Reset produces
Power-On-Reset for MSC8102.
SW10
Host Hard Reset
HRESET
SW11
Host Soft Reset
SRESET
Pressing button SW11 results in Soft Reset for
MSC8101. Despite the reset, clock and chip-select
data as well as SDRAM contents are retained. Soft
Reset causes the Host’s core to run free despite
the position of SW6/8.
Pressing and releasing button SW12 results in an
non-maskable interrupt for MSC8101.
SW12
Host NMI (IRQ0)
ABORT
3.1.2 Jumpers
MSC8102ADS jumpers will be noted in the following sub-sections:
3.1.2.1 JP1 - External Power for CODEC
JP1 selects the source for the CODEC Power Rail. When a jumper is located between pins 1 2 of JP1 (Factory Set) then the CODEC feeds from the 3.3V plane of the ADS.
When a jumper is removed the 3.3V @ 200 mA external low-noise power supply may be connected to JP1 pins 2-3 as illustrated below in. Figure 3-2 JP1 - CODEC Power Selection.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
29
Configuration and Installation
1
JP1
1
GND
NORM
JP1
GND
NORM
3.3V
3.3V
Factory Set
JP1: 1-2 Close
+3.3V GND
External Power Supply
Figure 3-2 JP1 - CODEC Power Selection
3.1.2.2 JP2,JP3 - EE0,EE1 for Slave
JP2 and JP3 may be used for debugging purposes - to measure/set MSC8102 signal logic levels.l
JP2
JP3
1
1
EE0
EE1
Factory Set
JP2,3 Open
Figure 3-3 JP2,JP3 - EE0s,EE1s control
3.1.2.3 JP4 - Slave Clock Input Source
JP4 is used to select clock input source for MSC8102 either mounted on socket clock oscillator or
external pulse generator via P2 SMB connector.
1
1
JP4
OSC
EXT
Factory Set
JP4: 1-2 Close
JP4
OSC
EXT
External Clock Source
JP4: 2-3 Close
Figure 3-4 JP4 - MSC8102 Clock Source Select
3.1.2.4 JP5 - External Clock Enable for MSC8102 TDM port
JP5 is used for MSC8102 TDM port test purposes. In the instance that jumper JP5 is closed,
the TDM lines connect to the TSI & E1/T1 Framer devices and from there to expansion connector
J5. If jumper JP5 is open then all TDM signals become available on J5 and, as a consequence,
30
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Configuration and Installation
are isolated from other ADS sections..
1
JP5
CLK MST
Factory Set
JP5 Close
Figure 3-5 JP5 - TDM External Clock Enable
3.1.2.5 JP6 - CT-Bus Master Reset Enable
If the JP6 is closed then the MSC8102 applies Master Reset for the CT-bus (H.110)..
1
JP6
CTRST
Factory Set
JP6 Open
Figure 3-6 JP6 - CT-Bus Master Reset Enable
3.1.2.6 JP7 - ADS PON Reset Enable
If JP7 is closed then the ADS exists in a Power-On-Reset state that is used solely for debugging
purposes..
JP7
1
PRST
Factory Set
JP7 Open
Figure 3-7 JP7 - ADS PON Reset Enable
3.1.2.7 JS1-3 - Current Consumption Measurement
JS1 to 3 reside, respectively, on the following: the core; the PLL; and, the I/O-pin’s main flow.
To measure current consumption the relevant JS must be removed using a soldering tool. Follow-
MSC8102ADSUM/D Ver. 1.2
User’s Manual
31
Configuration and Installation
ing this a current meter (or a shunt) is connected using the shortest and thickest wires available.
Warning
The delicate task of removing JS1 to 3 should
only be performed by a skilled technician. The
MSC8102ADS may suffer permanent damage if
an unskilled hand makes more than 3 attempts
at the change.
3.1.2.8 JG1-5 GND Bridges
The MSC8102ADS has 5 bridges designated as GND. They are meant to assist in general measurements and act as logic-analyzer connections.
Warning
Use only INSULATED GND clips when connecting to a GND bridge as, otherwise, permanent
damage may occur to the MSC8102ADS. Non-insulated clips coming into contact with surrounding “HOT” points may create short-circuits.
3.1.2.9 TP13 - Slave Clock Output
Using a scope, TP13 may be utilized for measuring a MSC8102 System Bus Clock.
CLKOUT
Figure 3-8 TP13 - MSC8102 ClockOut
3.1.3 LEDs
The MSC8102 has the following LEDs:
3.1.3.1 LD1 - Slave in Debug Mode
The debug acknowledge function of the EE1 pin found on the MSC8102 is indicated by a green
LED, LD1. When lit, the MSC8102 is either in Debug Mode or there is a high level of EE0 input
(debug request).
3.1.3.2 LD2 - CODEC
A yellow LED, LD2, indicates that the CODEC device is ready for programming. The CODEC
is controlled by bit BCSR0.3.
32
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Configuration and Installation
3.1.3.3 LD3 - Slave is running
A green LED, LD3, indicates that the MSC8102 is accessing the external System Bus by reading/writing to the bus devices.
3.1.3.4 LD4 - Host is running
A green LED, LD4, indicates that the MSC8101 is accessing the external 60-x bus by reading/writing to the bus devices.
3.1.3.5 LD5 - RS232-1 Enable
A yellow LED, LD5, indicates whether the Host’s RS232 Transceiver has been enabled (lit) or
disabled. The RS232 is controlled by bit BCSR1.6.
3.1.3.6 LD6, LD7 - Host Signaling LEDs
LED’s, LD6 (red) and LD7 (green), are program controlled. They are used for extra visibility on
the Host- running utility. They are lit up by setting bits BCSR0.6-7.
3.1.3.7 LD8 - RS232-2 Enable
An activated yellow LED, LD6, indicates that the Slave RS232 Transceiver is enabled. If disabled, the MSC8102 UART pins may be used for off-board applications via the J5 expansion connector. The RS232 is controlled by bit BCSR1.7.
3.1.3.8 LD9, LD10 - Slave Signaling LEDs
LED’s LD9 (red) and LD10 (green) are MSC8101 program controlled. They are used for extra
visibility on the Slave MSC8102 running utility. The LED’s are lit by setting bits BCSR0.4-5.
3.1.3.9 LD11 - External Power Indicator
When the ADS is inserted into the cPCI rack, a green LED, LD11, indicates a 5V presence from
the backplane power supply. The ADS is powered from the backplane power supply whenever the
SW8 Power Switch has been turned to the “OFF” (down) position.
3.1.3.10 LD12 - 3.3V Power Indicator
A 12V power supply is plugged into the P23 Power Connector on the board’s front side. The
ADS is powered by the 12V power supply when the SW8 Power Switch is turned to the “ON” (up)
position. The green LED, LD12, indicates a 3.3V power level (from the available 12V power
supply).
3.1.3.11 LD13, LD14 - Ethernet Indications
The green LED, LD13, indicates a 100MBps operation mode. The green LED LD14 indicates
a full duplex mode. Two additional Ethernet LEDs are mounted inside connector P20 RJ45 - a
green LED indicative of an existing “LINK” as well as a red LED that serves as a ”COLLISION”
indicator.
3.1.3.12 LD15, LD16 - 1.5V Power Indicator
Green LED’s, LD15 and LD16 indicate, respectively, the presence of a 1.5V power supply for
MSC8102ADSUM/D Ver. 1.2
User’s Manual
33
Configuration and Installation
the core and PLL of the Host and Slave processors.
34
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Configuration and Installation
3.2 Installation Options
Configure the ADS board according to its environment:
•
Host Controlled Operation through OnCE port
•
Stand-alone mode
3.2.1 Debug Connection Schemes
In the Debug Connection Scheme configuration the MSC8102ADS is controlled by a host
computer via the OnCE Port, a subset of a JTAG port. This configuration allows for extensive debugging using an on-host debugger. The Host is connected to the ADS via a Command Converter
provided by a third party such as Macraigor Systems. A PCI host debug interface is preferred due
to the faster throughput offered by a parallel port interface. Three possible connections are shown
in the figures below: Figure 3-9 Host System Debug Scheme A (spitted), Figure 3-10 Host System
Debug Scheme B (daisy-chained) and Figure 3-11 Host System Debug Scheme C (daisy-chained).
.
Host
Computer1
Host
Computer2
Command
Converter2
PC/SUN
PCI I/F
OnCE
PCI I/F
8102ADS
P14
Command
Converter1
PC/SUN
14 Wire
Flat Cable
8101
P15
8102
14 Wire
Flat Cable
Figure 3-9 Host System Debug Scheme A (spitted)
PC/SUN
PCI I/F
Command
Converter
8102ADS
P14
14 Wire
Flat Cable
OnCE
Host
Computer
TDI
TDO
8101
8102
TDO
TDI
Figure 3-10 Host System Debug Scheme B (daisy-chained)
MSC8102ADSUM/D Ver. 1.2
User’s Manual
35
Configuration and Installation
8102ADS
PCI I/F
14 Wire
Flat Cable
OnCE
P14
Command
Converter
PC/SUN
TDI
TDO
TDO
8101
TDI
8102
To ext. boards
Host
Computer
cPCI
Figure 3-11 Host System Debug Scheme C (daisy-chained)
Figure 3-12 JTAG-Chain on Backplane, below, illustrates a debug configuration. This debug
configuration enables evaluation of the DSP farm concept. The concept sees one ADS Host processor (MSC8101) with Slave (MSC8102) and three ADSs Slaves (MSC8102) placed on a total of
four boards. These boards are then mounted onto a standard CompactPCI® backplane that
provides required interconnections.
The EE-pins, EE0 and EE1, of the MSC8102 are placed on the ADS front panel. When these
pins are connected, as shown below in Figure 3-12, all the slaves simultaneously enter Debug
mode. The connection is made by a specific (made-to-order) pin-to-pin cable..
System
Slot
Prph.
Slot1
J1
Prph.
Slot3
J1
J1
D2
E2
D2
E2
D2
E2
OnCE2
ADS
2
TDI TDO
TDI TDO
8101
8102
OnCE
OnCE1
1
OnCE
3
TDI TDO
TDI TDO
8102
8102
ADSs
ADSs
1
EE0 EE1
EE0 EE1
EE0 EE1
External cable to connect EE0,1 pins
1,2,3 - three types of chains: separate, short and long
Figure 3-12 JTAG-Chain on Backplane
36
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Configuration and Installation
3.2.2 Standalone Operation
In the standalone mode, the Host does not control the ADS via the OnCE port. Rather, the ADS
may be connected to the Host via alternate ports - RS232 (either from Host or from Slave), Fast
Ethernet, ATM155, etc. Operating in standalone mode necessitates burning the application
program into the board’s Flash memory (either the Host’s or the Slave’s). In the instance of a single
board configuration, the DSI bus is used to connect with the Host.
et
rn
he ork
t
E etw
N
HOST BUS (backplane)
DSI
8102
Eth
J1
I/F
)
tic
Op
(
5
15
M
T
A
ATM
8101
Host
Computer
E1/T1
J2
.
E1/T1
CODEC
TSI
RS232
x2
RS
J4
232
Voice
H.110
HOST BUS (backplane)
Figure 3-13 Standalone Configuration (ADS board)
E1/T1
J1
E1/T1
DSI
Host
Computer
8102
J2
RS232
CODEC
RS232
.
TSI
J4
Voice
H.110
Figure 3-14 Standalone Configuration (ADSs board)
The 60-x bus of an MSC8101 or an MPC8260 may be used as the host bus for the Single board
(ADSs) standalone configuration. The ADS can provide a direct connection through the J1/J2 con-
MSC8102ADSUM/D Ver. 1.2
User’s Manual
37
Configuration and Installation
nectors to the DSI bus of the MSC8102 on the ADSs board. To this purpose it is possible to use a
general 6U CompactPCI® rack with a single system board such as the ADS and several ADSs
boards.
3.3 Connecting the ADS Board
The ADS board should be resides at working desk in a convenient place for connecting it to the
Host computer and external power supply.
Connect the ADS as follows:
38
1)
Connect the External Command Converter to the front “OnCE” (P14 ) connector for B
and C debug scheme (Figure 3-10 and Figure 3-11) and to P14 and/or to header P15
for A debug sheme (Figure 3-9).
2)
Connect an external power supply to P23 power jack on the ADS.
3)
Plug in the external power supply to the ~110-240VAC wall outlet.
4)
Switch on SW8 Power on the ADS board, upper LED “PWR” (LD12) will lights up.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Configuration and Installation
3.4 Power Supply
The MSC8102ADS requires +12VDC @ 1.8A max, power supply. The power may be provided
via cPCI expansion connectors when the ADS is placed into backplane.
To apply power source insert enclosed power supply plug into the P23 Power Jack on the board
as shows in the Figure 3-15 Ext Power Supply Connection.
MSC8102ADS
~100-240V
47-63Hz
AC/DC
Power Supply
P23
PS-1218APL05
12VDC Input
12V,1.8A
P23
“+” Terminal
“-” Terminal
Figure 3-15 Ext Power Supply Connection
NOTE:
It is allow to connect users hardware applications to the ADS board using
cPCI Expantion Connectors J1,J2,J4,J5 connectors. Therefore, take
additional power requirements into consideration when using an enclosed
power supply.
In order the ADS is inside cPCI rack power may be applied from build-in power supply when
ADS switch SW8 is turned to the “OFF” (down) position as shows in the Figure 3-16 Power on
Backplane. On Front Panel lower “PWR” LED indicates that power from backplane is “good”.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
39
Configuration and Installation
cPCI Rack
ADS Front Panel
ON
Power Supply
Figure 3-16 Power on Backplane
40
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Functional Description
Section 4 Functional Description
4.1 General
This chapter describes, in detail, the ADS block diagram. There are two ADS configurations
based on MSC8102. The full ADS configuration, MSC8102ADS, consists of two sides: the Host,
based on MSC8101 as host controller; and, the Slave, based on the MSC8102. The second configuration is a single board based on only one processor, the MSC8102.
The MSC8102 is interfaced to the Host via a DSI bus that is connected asynchronously to the
60-x bus of the MSC8101. The DSI bus is accessible to external tools via the J1/J2 expansion connectors. An additional expansion connector, J5, provides connectivity to four TDM ports - the
UART, the Timers, the Interrupts and the GPIO of the MSC8102. The J4 expansion connector interfaces with the standard H.110 bus (ECTF H.110 Specification). The 32-bit DSI data bus (default) may be reconfiged during Power-on-Reset to 64-bit. At the same time, the 64-bit System
Data Bus becomes 32-bit.
The address bus switch for the SDRAM is located on the MSC8102’s System Bus. This switch
provides correct connections for both the 64-bit and 32-bit data bus configurations.
4.2 Reset & Reset - Configuration
The Reset signals for the MSC8102ADS are produced by either the MSC8101 or MSC8102
controllers. Reset circuitry details are shown below in Figure 4-1 "ADS Reset Diagram":
From
Power Supply
PORESET
PU
3.3V
1.5V(h+s)
uP
Supervisor
8101
8102
PORESET
HRESET
PU
PORESET
SRESET
PU
HRESET
PU
SRESET
PU
60-x Bus
BCSR Logic & Register
RESET
HRST1
HRST2
HRESETh
SRESETh
HRESETs
SRESETs
MSC8101
MSC8102
HRST3
Reset either from or to other boards.
Figure 4-1 ADS Reset Diagram
MSC8102ADSUM/D Ver. 1.2
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41
Functional Description
4.2.1 Power-On-Reset
The MSC8102ADS main Power-On-Reset button initializes both the Host processor and the
Slave state after power up. The initialization involves dedicated logic that uses MAX6827 - a dual
uP supervisor looking after one 3.3V and two 1.5V power rails that keep the processors supplying
nominal power. The dual uP supervisor has open-drain output circuitry that allows for off-board
RESET sources such as the one-shot. The PORESET impulse for the MSC8102 is driven by
BCSR logic and will either be asserted during MSC8101 HRESET or activated by programming
the BCSR register. See Table 4-11 "BCSR2 Register Description" on page 66 for details.
Main Power-On-Reset is asserted to the MSC8101 for a period of 350msec. This provides
ample time to cover voltage regulator stabilization. Power-On-Reset may be generated either
manually or by a dedicated push-button connected to the manual reset input of the supervisor
device.
4.2.2 Host Power-On-Reset Configuration
Upon completion of the Power-On-Reset sequence the MSC8101 samples MODCK(1:3)
together with three additional clock configuration bits. In addition, various MSC8101 system (dsp
core, cpm, 60x bus) clock modes are set. The MODCK(1:3) combination options are controlled by
DIP Switches SW6/1-6 and are buffered via BCSR logic.
Following Power-On-Reset is the Hard Reset sequence within which a multitude of other
options are configured. MODCK bits are sampled during Hard Reset configuration as well as each
time a Hard Reset sequence is entered, however, they are influential only once - after Power-OnReset. If a Hard Reset sequence is later entered then the bits, though sampled, have no impact.
4.2.3 Slave Power-On-Reset Configuration
Upon concluding the Power-On-Reset sequence the MSC8102 samples the MODCK(1:2)
together with three additional clock configuration bits. It should be noted that various MSC8102
system (dsp cores, 60x bus) clock modes are also set. MODCK(1:2) combination options are controlled by DIP Switches SW4/1-2 and are buffered via BCSR logic. At the time of Power-On-Reset
some pins will be sampled. The complete setting can be seen in Table 4-3. The Reset signals for
the MSC8102ADS are produced by either the MSC8101 or MSC8102 controllers. Reset circuitry
details are shown above in Figure 4-1 "ADS Reset Diagram". MSC8102 may also be configured via Host MSC8101 by writing the Power-on-Reset Configuration to BCSR and setting bit
BCSR1.0 (RECONF) to 0. This will invoke secondary Power-On-Reset for the MSC8102.
Following Power-On-Reset is the Hard Reset sequence within which a multitude of options are
configured. MODCK bits are sampled during Hard Reset configuration as well as during the first
Hard Reset sequence after a Power-On-Reset. However, during subsequent Hard Reset sequences the bits are sampled but deemed irrelevant.
4.2.4 Hard/Soft Reset Capabilities
Host processor Hard Reset is available in the debug mode via JTAG/ONCE with a command
from the host debugger system, Metrowerks CodeWarrior (CW). When Host HRESET is asserted
then a MSC8102 PORESET impulse is generated automatically via BCSR logic. This occurs
despite the reset systems for both processors, Host and Slave, being electrically isolated.
Dedicated push buttons facilitate manual Hard and Soft Reset for processors MSC8101 and
MSC8102. These buttons enable run-time reset when the Command Converter is disconnected
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Functional Description
from the MSC8102ADS.
The HRESET lines may be internally driven by the MSC8101/MSC8102 and as such must be
driven to the MSC8101/MSC8102 with an open-drain gate.
When generating Hard Reset the registers of both processors are completely reset. For
example, the Hard Reset configuration is re-sampled and all registers, including memory controllers but excepting PLL’s, are reset. The reset results in a loss of dynamic memory content.
Off-board Slave DSP (max. of 4) Hard Reset signals are present in inputs from the BCSR register. Through programming, this allows for the separate monitoring and assertion of 8102 Slave
resets.
4.2.5 Hard Reset Configuration
Hard Reset configuration is performed for both the Host (MSC8101) and Slave processors
(MSC8102). In the case of the Single Board (ADSs), the Hardware Configuration Word (HCW) will
be taken from the System bus to the MSC8102 device.
4.2.6 Host Hard Reset Configuration
Hard Reset, applied both externally and internally to the MSC8101, samples the HCW. The
configuration word may originate from an internal default if the RSTCONF signal is negated during
an HRESET assertion. It may also be taken from the 8101 Flash memory (MS 8-bits of the data
bus) or from the BCSR board registerA in the instance that the RSTCONF signal is asserted along
with the HRESET.
If the 8101 Flash has been tampered with, then the default configuration word will be taken from
either the Flash or the BCSR. A dedicated jumper determines whether the source of the default
configuration word will be the FLASH or the BCSR.
During the Hard Reset sequence the configuration master reads, one byte at a time, the Flash
(or BCSR) memory at addresses 0, 8, 0x18, 0x20 in order to assemble the 32-bit configuration
word.
Table 4-1 Effect of Host (MSC8101) Pins on the Power-on-Reset Configuration
Name of signal
Value
MODCK[1:3]
‘101’
RSTCONF
EE0
EE1(HPE)
EE[4:5](BTM[0:1])
Mode
Implementation
Set clock mode 40 (MSC8101 rev1)
DIP Switch SW6/1-3 setting.
May be controlled by BCSR
logic
0
Boot Master from 60-x bus
Pulled-down permanently
0
Core running free after Hard Reset
1
Core enters Debug mode after Hard
Reset
DIP Switch SW6/8 setting
(Debug Enable/Disable)
via BCSR buffer
0
Host Port Disable - 60-x bus configured
for 64-bit
Pulled-down permanently
Boot Source resides at 60-x bus
Pulled-down permanently
‘00’
DIP Switch SW6/8 controls the EE0 pin in order to provide a post-reset manual debug capability
A. In general, reading from any device residing on CS0.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
43
Functional Description
(Debug Request).
Table 4-2 "MSC8101 Hard Reset Configuration Word (HCW1)", below, describes the
field values of the Hard Reset configuration word:
Table 4-2 MSC8101 Hard Reset Configuration Word (HCW1)
Data
Bus
Bits
Prog
Value
[Bin]
EARB
0
’0’
Internal Arbitration Selected.
EXMC
1
’0’
Internal Memory Controller. CS0 active at
system boot.
IRQ7INT
2
’1’
INT_OUT function is active
EBM
3
’0’
Single chip bus mode is assumed
BPS
4:5
’10’
16-bit Boot Port Size for both Flash memory
and BCSR
SCDIS
6
’0’
SC140 enabled
ISPS
7
‘0’
Internal space port size for external master
access is 64-bit. Not of concern as the current
board configuration does not support this
feature.
IRPC
8:9
’00’
Interrupt
pin
configuration.
RES/
BADDR(29)/IRQ2,RES/BADDR(30)/IRQ3,
RES/BADDR(31)/IRQ5 are selected as RES
(not connect)
DPPC
10:11
‘00’
Data Parity Pin configuration as IRQ[1:7].
12
’0’
NMI interrupt is serviced by the core.
13:15
’000’
Reserved
16
’0’
Reserved. Non-functional cleared bit.
BBD
17
’0’
Bus busy pins set as: ABB/IRQ2 pin is ABB
DBB/IRQ3 pin is DBB
MMR
18:19
‘11’
External Bus Request masked.
Reserved
20:21
‘00’
Reserved. Must be cleared
TCPC
22:23
’10’
Transfer code pins are configured following
PORESET:
MODCK1/BNKSEL(0)/TC(0) as BKSEL0
MODCK2/BNKSEL(1)/TC(1) as BKSEL1
MODCK3/BNKSEL(2)/TC(2) as BKSEL2
Field
NMIOUT
ISB
44
Implication
Offset In
HCW
source
[Hex]
Value
[Hex]
0
28
8
00
10
32
IMMR initial value 0xF000_0000, i.e., initially
the internal space resides at this address.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Functional Description
Table 4-2 MSC8101 Hard Reset Configuration Word (HCW1)
Data
Bus
Bits
Prog
Value
[Bin]
24:25
’00’
Buffer control 1-pin configuration BCTL1/
DBG_DIS functions as BCTL1
Reserved
26
’0’
Reserved. Should be cleared.
DLLDIS
27
’1’
DLL off
28:30
‘111’
31
’0’
Field
BC1PC
MODCK_Ha
Reserved
Implication
Offset In
HCW
source
[Hex]
Value
[Hex]
18
1E
High-order bits of the MODCK. Clock
configuration scheme 57 for MSC8101
Reserved. Should be cleared.
a. Applied only once after power-up reset.
4.2.7 Slave Reset Configuration
The primary h/w setting, using two DIP Switches, will configure the MSC8102 after power-up.
The following modes are available:
•
System Mode - the configuration word is fetched and boot is achieved via the system bus
in the master mode (DIP Switch SW4/3 is in “SYS” position).
•
DSI Mode - configuration word is written by host; boot is completed via the system bus in
the Slave mode (DIP Switch SW4/3 in “DSI” position).
•
DSI bus width of either 64-bit or 32-bit is chosen by the DIP Switch SW7/3.
See Table 4-3 "MSC8102 Pins Dependant upon Power-on-Reset Configuration" on
page 46 for further details.
The MSC8102 may be reconfiged on demand when the Host processor programs the BCSR
register with the desired configuration setting and invokes a Power-on-Reset or Hard Reset
sequence for the MSC8102. This setting is called a secondary reset configuration. MSC8102 Hard
Reset configuration may also be achieved manually by pressing the Hard Reset Push button
MSC8102ADSUM/D Ver. 1.2
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Functional Description
4-2 "Secondary Reset Configuration Details" below.
RSTCONF
CNFGS
SWTE
DSI64
DSISYNC
MODCK[1:2]
BTM[0:2]
PORESET
HRESETs
SRESETs
8101
60-x bus
8
SYS -1 -2
CHIP-ID[0:3]
DSI
SW7
MODCK-
BCSR
Config Depended pins
(HRESETs). See Figure
8102
EE[0:1]
DEBUG
ON
2
3
EE1
PU
HRESETh
SRESETh
HRESETs
4
PU
SRESETs
PU
To P2:GA[0:3]
EE0h EE0s
EE0 = EE1ex || EE0sw
PD
EE1 from
another board
EE1 to
another board
Figure 4-2 Secondary Reset Configuration Details
Note the MSC8102 Reset configuration setting found below. The MSC8102 Reset configuration
may be loaded in two ways. Either by the Host or, depending upon the DSI or SYS mode, taken
from the device connected to the CS0 of the MSC8102 System bus (Slave-side Flash).
Table 4-3 MSC8102 Pins Dependant upon Power-on-Reset Configuration
Name of signal
MODCK[1–2]
Value sampled
at pins
‘00’ or ‘01’
Primary Mode
Implementation
Clock mode 0 or clock mode 1.
DIP Switch SW4/1-2 primary setting or
driven by the BCSR for secondary
setting.
RSTCONF
‘0’
Configuration Master
System or DSI bus.
from
the
CNFGS
‘0’
Configuration
System bus.
from
the
‘1’
Configuration Master from the DSI
bus.
‘0’
Software Watchdog Timer Disable
Set logically if DSI is config master.
‘1’
Software Watchdog Timer Enable
Set logically if System Bus is config
master.
SWTE
46
Master
MSC8102ADSUM/D Ver. 1.2
User’s Manual
DIP Switch setting
Functional Description
BTM[0:2]
DSI64
‘000’
Boot from the 60-x bus
‘001’
Boot from the DSI
‘0’ or ‘1’
DSISYNC
‘0’
CHIP_ID[0–3]
‘1111’
Configuration modes controlled by DIP
Switch SW4/3 setting.
32-bit DSI data bus with 64-bit
System data bus or visa versa.
Controlled by DIP Switch SW7/3.
DSI set in Asynchronous mode
Pulled-down permanently.
Chip ID encoded to ‘0xF’
Pulled-up permanently. Prepared for
backplane application. For multi-chip
(multi-board) system, ID will be set
according to slot’s GA (geographic
address).
Table 4-4 MSC8102 Hard Reset Configuration Word (HCW2)
Data
Bus
Bits
Prog
Value
[Bin]
EARB
0
’0’
Internal Arbitration selected.
EXMC
1
’0’
Internal Memory Controller. CS0 active at
system boot.
INTOUT
2
’1’
INT_OUT function is active.
EBM
3
’0’
Single chip bus mode is assumed.
BPS
4:5
’01’
8-bit Boot Port Size for the Slave Flash
memory.
SCDIS
6
’0’
SC140 enabled.
ISPS
7
‘0’
Internal space port size for ext. master
access is 64-bit. Not an issue as this feature is
not supported in the current board
configuration.
IRPC
8
’0’
Interrupt pin configuration. BADDR(29)/
IRQ5, BADDR(30)/IRQ2, BADDR(31)/IRQ3
are selected as interrupt pins.
Reserved
9
‘0’
Reserved. Must be cleared
10:11
‘10’
Data Parity Pin configuration. NC/DP0/
DREQ1/EXT_BR2, IRQ1/DP1/DACK1/
EXT_BG2, IRQ2/DP2/DACK2/ EXT_DBG2,
IRQ3/DP3/DREQ2/ EXT_BR3, IRQ4/DP4/
DACK3/ EXT_BG3, IRQ5/DP5/DACK4/
EXT_DBG3, IRQ6/DP6/DREQ3, IRQ7/DP7/
DREQ4 are selected as DMA pins: DREQ1,
DACK1, DACK2, DREQ2, DACK3, DACK4,
DREQ3, DREQ4.
NMIOUT
12
’0’
NMI interrupt is serviced by the core.
ISBSEL
13:15
’000’
Field
DPPC
Implication
Offset In
HCW
for system
sourcea
Value
[Hex]
0
24
8
20
IMMR initial value 0xF000_0000. i.e., the
internal space initially resides at this address.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
47
Functional Description
Table 4-4 MSC8102 Hard Reset Configuration Word (HCW2)
Data
Bus
Bits
Prog
Value
[Bin]
Reserved
16
’0’
Reserved. Non-functional cleared bit.
BBD
17
’0’
Bus busy pins set as: ABB/IRQ4 pin is ABB
DBB/IRQ5 pin is DBB.
MMR
18
‘1’
External Bus Request masked.
Reserved
19
‘0’
Reserved. Must be cleared.
TTPC
20
‘0’
Transfer Type Pin Configuration. TT[0]/NC,
TT[2]/CS5, TT[3]/CS6, TT[4]/CS7 are chosen
as transfer type pins: TT[0], TT[2], TT[3], TT[4].
CS5PC
21
‘1’
Chip Select 5 Pin Configuration. CS5/
BCTL1 pin is configured as BCTL1.
22:23
’10’
Transfer code pins are configured after
PORESET:
TC0/GPIO0/ BNKSEL0 as BNKSEL0
TC1/GPIO1/ BNKSEL1 as BNKSEL1
TC2/GPIO2/ BNKSEL2 as BNKSEL2
LTLEND
24
‘0’
Defines the Host Endian mode as Big Endian.
PPCLE
25
’0’
PowerPC Little Endian Mode. Unimportant
while the Host is Big Endian (bit LTLEND is
zero).
Reserved
26
’0’
Reserved. Should be cleared.
DLLDIS
27
’1’
DLL off.
28:30
‘010’
31
’0’
Field
TCPC
MODCK_Hb
Reserved
Implication
Offset In
HCW
for system
sourcea
Value
[Hex]
10
26
18
14
High-order bits 3:5 of the MODCK. Default
Clock mode is 11.
Reserved. Should be cleared.
a. For the DSI source a 32-bit Configuration Word is written at offset 0x261BE050
b. Applies only ONCE after power-up reset.
4.3 Clock Source
4.3.1 Host Main Clock Scheme
MSC8101 requires a single clock source for the main clock oscillator. The [email protected] clock
oscillator is mounted on the 8-pin DIP socket (half-size form factor) for ease of replacement. All
MSC8101 60-x bus timings are referenced to the DSP output clock. CLKOUT is driven to a zero
delay buffer in order to split the load between the clock consumers on the board. One channel is
relegated to the MSC8101 DLL input in order to eliminate wire propagation delay to the SDRAM
devices.
An optional pulldown resistor is capable of transforming the Clock Zero Delay (ZD) Buffer into
48
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User’s Manual
Functional Description
a regular clock buffer when the internal PLL is disabled. In such a case the typical propagation
delay of the clock buffer may reach 7ns.
If the ADS is set with the ZD Buffer as default, then the MSC8101 must be configured with DLLoff. See HCW1 in Table 2-2. On the other hand, if the ZD Buffer is disabled (clock buffer mode)
then the MSC8101 must be configured with DLL-on in order to function properly with SDRAM.
ch1
SDRAM1-2
MSC8101
CY2309
CLK OSC
55 MHz
ZD
CLKIN
SDRAM1-1
CLKOUT
BUFFER
DLL_IN
BCSR
SYSCLK (to exp)
CLKM1
CLKM2
3.3V
S2
S1
To LA
Connectors
CLKM3
ch8
PD
Figure 4-3 Host Clock Distribution Scheme
4.3.2 Slave Main Clock Scheme
MSC8102 requires a single clock source for the main clock oscillator. For ease of replacement
the 41.6MHz @3.3V clock oscillator is mounted on the 8-pin DIP socket (half-size form factor). All
MSC8102 system bus timings are referenced to the DSP output clock. CLKOUT is driven to a ZD
Buffer in order to split the load between the clock consumers on the board. One channel reaches
the MSC8102 DLL input in order to eliminate wire propagation delay to the SDRAM device.
An optional pulldown resistor is capable of transforming the ZD Buffer into a regular clock buffer
when the internal PLL is disabled. In such a case the typical propagation delay may reach up to
7ns.
If the ADS is set with the ZD Buffer as default, then the MSC8102 must be configured with DLLoff. See HCW2 in Table 2-4. On the other hand, if the ZD Buffer is disabled (clock buffer mode)
MSC8102ADSUM/D Ver. 1.2
User’s Manual
49
Functional Description
then the MSC8102 must be configured with DLL-on in order to function properly with the SDRAM.
ch1
SDRAM2-2
MSC8102
CY2309
CLK OSC
41.6 MHz
ZD
CLKIN
SDRAM2-1
CLKOUT
BUFFER
CLKS1
CLKS2
To LA
Connectors
DLL_IN
3.3V
S2
S1
ch5
PD
Figure 4-4 Slave Clock Distribution Scheme
4.4 60-x Bus Buffering and Muxing
In order for the 60-x bus to achieve peak performance, it’s capacitive load must be reduced as
much as possible. As a consequence the slower devices on the bus (i.e. the Flash, ATM SONET
Framer M/P interface, BCSR and external tool bus) are buffered while the SDRAM devices and
the MSC8102 DSI side are not buffered.
Buffers are provided over address and, where necessary, strobe lines. The buffers used are
from the 74LVC family (by Texas Instruments) which operate on 3.3V although are 5V tolerantA.
All the expansion bus lines (64bit data @29 address lines + strobes) are also buffered. In order to
reduce noise and reflections, serial damping resistors are added to selected MSC8101/MSC8102
strobe lines.
Transceivers are provided for data and are only open under two conditions - when access to a
validB buffered board address exists or during a Hard Reset configuration sequence C. For
example, data conflicts are avoided when unbuffered or off-board memory is read, provided it is
not mapped to a valid board address. The user can avoid such errors through correct programming
of the Memory Controller.
The MSC8102 DSI bus provides additional configuration options in the form of different sized
data buses: 64-bit or 32-bit. The ADS is configured by the DIP Switch SW7/3 that sets the system
bus to 64-bit (SYS64 position) and the DSI bus to 32-bit. The opposite configuration, also using
the DIP Switch SW7/3 setting, pertains to data bus width distribution: system bus at 32-bit and DSI
bus at 64-bit. See Table 1-1 "The ADS Switches" on page 15. To achieve this connectivity a
bus switch device is utilized. See Figure 4-5 below:
A. Required for Flash and BCSR
B. An address which is covered in a Chip-Select region, that controls a buffered device by BCSR logic.
C. To enable activation of a configuration word stored in the Flash memory or BCSR.
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Functional Description
SDRAM2-2
8101
D[63:0]
32 LSB
32 MSB
32-bit
Bus
Switch
CKE
8102
32
HD[63:32]
System Bus/
DSI Bus
OE
BCSR controlled
HD[31:0]
DSI Bus
A[29:11]
HA[29:11]
A[10:7]
HCID[3:0]
DQM[0:3]
DQM[4:6]
HDBS[0:3]
2:1x4
HDBS[4:6]/
DQM[4:6]
CS3
HBCS
CS4
HCS
GPL2
HR/W
Figure 4-5 DSI Bus to 60-x Bus Connection
4.5 Chip Select Designation
The MSC8101/MSC8102 Memory Controller is used as a chip-select generator in order to
access on-board memory. The same functionality applies in the case of off-board memory,
however, in this instance access is achieved via J1/J2 expansion connectors. Consequences of
this usage are board area reduction, cost reduction, better power consumption and increased flexibility.
Instances exist when a Chip Select (CS) region, assigned to a bufferedA memory, is disabled
via the BCSR. This is undertaken so that local data transceivers are disabled when accessing a
given CS region and, consequently, possibleB contention over data lines is avoided. CompactPCI® expansion connectors J1/J2 carry lines of Memory Controller that are used for accessing
ADSs boards mounted on the peripheral slots of a CompactPCI® 6U backplane. This, as opposed
to the ADS board, that is present on the CompactPCI® 6U backplane system slot. The above
noted system configurations incorporate ADS and ADSs board connections and thus illustrates the
MSC8102 DSP-farm application when the MSC8101 acts as a host micro controller.
MSC8101 CS assignments for various MSC8102ADS memory/registers are outlined in Table
A. Buffers do not open when an unbuffered CS region is accessed.
B. During read cycles.
MSC8102ADSUM/D Ver. 1.2
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Functional Description
4-5 "Host Memory Controller Assignment".
Table 4-5 Host Memory Controller Assignment
MSC8101
Chip Select
Location
Assignment
Bus
Timing Machine
Flash, BCSR Config Word
60-x (Buffered)
GPCM
CS1
BCSR
60-x (Buffered)
GPCM
CS2
SDRAM1 bank
60-x (Unbuffered)
SDRAM Machine
HBCS(DSI broadcast)
60-x (Buffered+XBuffered)
GPCM
HCS(DSI select from 0 to 15)
60-x (Buffered+XBuffered)
UPMA
60-x (Buffered)
UPMB
60-x (XBuffered)
GPCM/UPMx(A or B)
-
-
CS3
CS4
External
CS0
ATM SONET Framer Microprocessor I/F
CS6
For off-board application.
CS7
Not supported on the ADS.
CS10
DSPRAM
Local PPC
UPMC
DSP Peripherals
Local PPC
GPCM
CS11
Internal
CS5
Table 4-6 Slave Memory Controller Assignment
Assignment
Bus
Timing Machine
CS0
Flash/BCSR Config Worda
60-x (Buffered)
GPCM
CS1
Not used/BCSRa
60-x (Buffered)
GPCM
60-x (Unbuffered)
SDRAM Machine
CS2
CS3
Location
External
8102 Chip Select
CS4
CS9
CS10
CS11
TSI
60-x (Buffered)
FALC T1/E1
60-x (Buffered)
Not supported on the ADS.
Internal
CS5-7
SDRAM2 bank
-
-
IP bus
Local PPC
GPCM
EFCOP
Local PPC
GPCM
L1’s & L2 Memory
Local PPC
UPMC
a. The BCSR function is only supported for ADSs board configurations.
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Functional Description
4.6 Local Interrupter
4.6.1 Host-side
External interrupts exist that are applied to the MSC8101:
1)
A specific-usage push button provides the source of the ABORT (NMI) signal.
2)
The Slave MSC8102 (INT_OUT) interrupt receives over line IRQ1.
3)
The ATM SONET Framer interrupt receives over line IRQ6.
4)
Available off-board interrupt sources from ADSs boards include lines IRQ2 to IRQ4.
5)
Ready/Busy Status of FLASH received over line IRQ7.
4.6.2 ABORT Interrupt to MSC8101
ABORT (NMI) is manually push-button generated. When the button is pressed, IRQ0 input is
asserted to the MSC8101. This type of interrupt is intended to support any resident debugger
usage made available to the MSC8102ADS.
4.6.3 Slave Interrupt
On-board Slave Interrupt Controller output is served by the Host interrupt, IRQ1. MSC8101 processor interrupt lines, IRQ2 to IRQ4, may be used to support up to three optional ADSs boards.
4.6.4 ATM SONET Framer Interrupt
Interrupt support of the ATM SONET Framer event report is achieved by connecting the interrupt output of the U30 ATM SONET Framer (INT) to the IRQ6 line of the MSC8101.
4.6.5 Flash Ready Interrupt
Output from the Ready/Busy Flash open-drain pin indicates whether a program/erase
Embedded Algorithm is still in progress or has been completed. Tying this output to interrupt line
MSC8102ADSUM/D Ver. 1.2
User’s Manual
53
Functional Description
IRQ7 allows for the simplification of the burning program that services Flash.
8101
IRQ0
IRQ5
IRQ1
IRQ6
IRQ2
IRQ3
IRQ4
ABORT
PU
Debounce
8102
BCSR
NMI_OUT
IRQ7
HOST
PU
INT_OUT
PU
PU
ATM SONET Framer
on-board
SLAVE
8102ADSs
PU
INT_OUT
PU
INT_OUT
INT_OUT
PU
FLASH1
PU
8102
Slot
2
8102
Slot
3
8102
RY/BY
Slot 4
Place in Backplane
Figure 4-6 Host Interrupt Utilization Diagram
4.6.6 Slave-side
Noted below are external interrupts applied to the MSC8102:
1)
A specific-usage push button provides the source of the ABORT (NMI) signal.
2)
TSI interrupt receives over line IRQ2 muxed with line BADDR31.
3)
FALC56 interrupt receives over line IRQ3 muxed with line BADDR30.
4)
Ready/Busy Status of FLASH received over line IRQ1.
4.6.7 ABORT Interrupt to MSC8102
ABORT (NMI) is manually push-button generated. When the button is pressed, IRQ0 input is
asserted to the MSC8102. This type of interrupt is intended to support any resident debugger
usage made available to the MSC8102ADS.
4.6.8 TSI Interrupt
The TSI interrupt request originates from IREQ output of Infineon’s SWITI device. The SWITI
54
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Functional Description
device has been configured as an open-drain and will be driven over line IRQ2.
4.6.9 FALC56 Interrupt
E1/T1 Framer (FALC56) interrupts are served by IRQ3. In this case the FALC56 has been configured as an open-drain output.
4.6.10 Flash Ready Interrupt
Output from the Ready/Busy Flash open-drain pin indicates whether a program/erase
Embedded Algorithm is still in progress or has been completed. Tying this output to interrupt line
IRQ1 allows for the simplification of the burning program that services Flash.
8102
IRQ0
ABORT
PU
Debounce
IRQ2
IRQ3
BCSR
IRQ1
SLAVE
TSI
PU
IREQ
E1/T1Framer
PU
INT
FLASH2
PU
RY/BY
Figure 4-7 Slave Interrupt Utilization Diagram
4.7 SDRAM
On the Host-side of the ADS is an unbuffered SDRAM bank that includes two Micron devices
with a total size of 16MB@64-bit.
The MSC8102 System Bus is powered by a SDRAM bank that includes the same two devices
found on the Host-side. The SDRAM bank may be configured at 16MB@64-bit with two SDRAM
parts for a full-width System Bus or at 8MB@32-bit with one SDRAM part for a half-size System
Bus. The SDRAM configuration feature is supported by BCSR logic that controls an address bus
mux device. The bus mux provides address line shifting as shown below in "".
MSC8102ADSUM/D Ver. 1.2
User’s Manual
55
Functional Description
PSDWE
BNKSEL[1]
A29
A0
A28
A27
A[29:19]
A2
A26
A20
PI3B33X257
CAS
W
W
A10
BA1
BA0
A(9:0)
A10
CKE
SYSCLK1
S
En
CAS
A(9:0)
PSDA10
3.3
A9
A19
RAS
BA0
A[0:9]
A3
RAS
BA1
BNKSEL[2]
A1
CS
CKE
SYSCLK2
CLK
PSDDQM[0:3]
MT48LC2M32B2
PSDCAS
CS
MT48LC2M32B2
PSDRAS
Bus Mux 12:24
SDRAM2-2
SDRAM2-1
CS2
CLK
DQM(0:3)
DQM(0:3)
DQ(31:0)
DQ(31:0)
HD[0:31]
32to64EN
from BCSR
PSDDQM[4:7]
D[32:63]
Figure 4-8 SDRAM Slave-side Connection Diagram
4.7.1 SDRAM Programming
In order to establish its mode of operation the SDRAM is, after power-up, initialized by means
of programming. The SDRAM is programmed by issuing a Mode Register Set command wherein
command data is passed to the Mode Register via the SDRAM’s address lines. The Mode Register
Set command is fully supported by the MSC8101/MSC8102 SDRAM machine.
in
The Mode Register programming value for Micron’s SDRAM MT48LC2M32B2-8 is noted below
Table 4-7 "SDRAM Mode Register Programming up to 100 MHz".:
Table 4-7 SDRAM Mode Register Programming up to 100 MHz
SDRAM
Address Linea
Value
Description
A10
Reserved
‘0’
Must program to zero
A9
WB (Write Burst Mode)
‘0’
Write Burst enabled
A8, A7
Operating Mode
‘00’
Standard Operation (default)
A6 - A4
CAS Latency
A3
A2 - A0 (LSB)
56
SDRAM Mode Reg Field
Burst Type
Burst Length
‘010’ or ‘011’
‘0’
’010’/’011’b
Program 2 or 3 CAS Latency depending on Bus
frequency
Sequential Burst Access
4/8 Word Burst Length (Beat count)
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Functional Description
a. In effect the SDRAM2-1 A0 will be connected to the MSC8102 A29/A28 address line (32/64 -bit System
bus width mode).
b. An 8-beat burst is programmed for the MSC8102 32-bit System Bus width.
4.7.2 SDRAM Refresh
SDRAM has an auto-refresh mode. For example, when using the first SDRAM Machine’s
periodic timer, an auto-refresh command is issued to the SDRAM every 15 µsec. Consequently all
4096A SDRAM rows are refreshed within spec’d 61.44 msec. The 2.56 msec interval of refresh
redundancy within the (spec’d 61.44 msec) window acts as a safety measure covering, for the
refresh controller, possible delays in bus availability.
4.8 Flash
MSC8102ADS will support the AMD flash device, Am29LV320 4MB volume. The Host-side
Flash is interfaced to a 16-bit buffered 60-x bus. The same Flash device type, found on the Slaveside, is configured by the hardware to an 8-bit mode. The Hardware Write Protect pin, found in both
the Host and Slave -side Flashes, is driven by BCSR logic and provides improved protection
against the accidental erasing of both the HCW and of the base boot code stored in the boot sector.
4.9 TDM Port Peripherals
Four MSC8102 TDM ports interface with the Infineon PEF24471 Time-Slot Interchanger. In
order to make the testability and flexibility features accessible to varying modes, all the TDM lines
go to expansion connector J5 of CompactPCI®. Note the general interconnection diagram Figure
4-9 below. Four MSC8102 TDM ports interface with the Infineon PEF24471 Time-Slot Interchanger. In order to make the testability and flexibility features accessible to varying modes, all the TDM
lines go to expansion connector J5 of CompactPCI®. Note the general interconnection diagram
and Figure 4-10 "TDM Clocking Diagram", below.
A. Each SDRAM component is composed of 4 internal banks each with 4096 rows. They are refreshed in
parallel.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
57
Functional Description
J5 Expansion Connector
T
T
T
T
T
OUT[3:5]
Infineon PEF24471 TSI
RSIG
XSIG
IN[7:10]
T
OUT[7:10]
PEB 2256
RFM
SCLKR
Infineon
Tdata[3]
Tsync[3]
Tclk[3]
Rdata[3]
Rsync[3]
Rclk[3]
GPCLK[0:1]
IN[0:2]
GPCLK[2]
GPCLK[3]
OUT[0:2]
GPCLK[4:6]
IN[3:5]
XDI
RDO
E1/T1 Framer
8102 TDM Ports
Tdata[0:2]
Tsync[0:2]
Tclk[0:2]
Rdata[0:2]
Rsync[0:2]
Rclk[0:2]
DSTo
DSTi
F0ib
C4ib
SYSCLK
MT92303
Mitel
Codec
SWITCH
T
4.096MHz
T
H.110
To J4
IN[6]
OUT[6]
GPCLK[7]
C4n
“T” denotes the capability of setting output Hi-Z in order to drive a signal from an external source
Figure 4-9 TDM Connection Diagram
8102TDM
TDMCLK[0:2]
PEF24471
TDMSYN[0:2]
Bus Switch
NETREF
H.110
XTALIN
16.384MHz
TDMSYN3
TDMCLK3
T_SYNC
FRMtoTSI
T_CLK
A/B
from BCSR
GPCLK2
GPCLK3
FALC56
Line
Interface
Framer
SYPR~
T1/E1
RL
SCLKR
XL
RCLK
RFM~
Clock
Adapter
MCLK
Figure 4-10 TDM Clocking Diagram
Figure 4-10 "TDM Clocking Diagram", above, depicts variant clocking configurations.
58
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Functional Description
The clock/sync has several modes. The first mode is an internal clock master based on the
16MHz clock oscillator’s source for all four TDM ports. The second denotes the T1/E1 network
master mode as provided for the third TDM port by the FALC56 E1/T1 Framer. The last available
clocking mode is a Slave to the CT-bus Master Clock’s synchronization of the Time Slot Interchanger (TSI) device.
4.9.1 Time Slot Interchanger (TSI)
The PEF24471 TSI device utilized on the ADS is a member of the SWITI family. It provides a
complete time slot switch and interface for the H.110 time division multiplexed (TDM) buses. The
PEF24471 TSI device can switch between local input and output buses as well as switch between
the H.110 bus and the local bus. The PEF24471 has a capacity of up to 2048 connections.
As well as supporting the newer H-MVIP and ECTF H. 1x0 standards, the TSI chip is backward
compatible to bus standards MVIP-90 and Dialogic's SC - Bus. Local streams may operate on 16
physical inputs and outputs. The data rates are programmable on each of the 32 physical streams
- the streams are selected in groups of four. The data rates are on a per stream basis as follows:
2.048 Mbits/s and 4.096 Mbits/s or 8.192 Mbits/s and 16.384 Mbits/s.
After buffering, the PEF24471 device interfaces at 8-bit to the MSC8102 System bus.
To view the program manual see [3].
4.9.2 E1/T1 Framer
Infineon’s FALC®56 Framer PEB 2256 supports one network line as well as containing analog
and digital function blocks configured and controlled by the MSC8102 Slave-side processor. The
FALC®56 Framer PEB 2256 has a multitude of implemented functions. As a consequence it is
suited to a wide range of networking applications and, further, fulfills all required interfacing
between analog E1/T1/J1 lines and the digital PCM system highway. See the connection schemes
found in Figure 4-9 "TDM Connection Diagram".
4.9.3 CODEC
The ADS uses the Mitel MT92303 Dual CODEC to provide complete audio to the PCM interfaces - including filtering and optional data “companding” as required by the ITU-T G.711 & G.712
recommendations. Two built-in amplifiers allow direct connection to a handset, headset, auxiliary
channel and microphone/speaker.
Three PCM Data Formats are available: 16-bit Linear; “companded” ITU-T A-law; and µ-law.
PCM data is transferred via a serial interface operating in the ST-bus mode. Though serial I/F is
programmed to an ST-bus mode, it is available for allocating data to any of the 32 available
channels and is easily interfaced to the local channel of the TSI device.
CODEC control and programming occur over a serial interface implemented by two MSC8102
GPIO’s and a CS pin. CS control is realized via the BCSR register bit. One GPIO functions as a
MSC8102ADSUM/D Ver. 1.2
User’s Manual
59
Functional Description
clock while the other acts as a bi-directional data path.
Table 4-8 CODEC Initialization
Byte
address
of
dual
Codec
in hex
Value in hex
Byte Name
Operation
Mode
Test
Mode
‘01’
‘03’
0,1
Control Register
2,3
CODEC Enable
4,5
Rx Hi-Pass-Filter
6,7
Sidetone Gain
‘00’
8,9
DSP Test
‘00’
0A,0B
0C
Tx Gain
Function
Action
Test: only Rx Enable or together with
Sidetone. PCM set in Linear mode.
A-Law.
Should be set
‘01’
CODEC enable, gain is 0dB.
Should be set
‘00’
Cut Off Frequency of RX Path
‘DSP’ Hi Pass Filter is 0dB.
Accept power-up
setting
‘0D’
Sidetone gain - 39dB for operation
mode or 0dB for test mode.
Dependent setting
‘01’
Digital side loopback for test mode.
Dependent setting
Tx gain is 0dB.
Accept power-up
setting
‘0’
Audio Interface
for Auxtone
‘CF’
AUXTONE gain is 0dB, Electret
Microphone Bias is 2.0V.
Should be set
Audio Interface
for three channels
‘CE’
Rx gain is 0dB, Electret Microphone
Bias is 2.0V.
Should be set
10
Audio Interface
Enable
‘73’
Enable Audio interface 0 and 1,
Voltage Reference and two Tx
Analog circuitry.
Should be set
11
Cross-Point
Selection
‘34’
Route CODEC 0 to Audio Interface 0
and CODEC 1 to Audio Interface 1.
Should be set
12
Codec Channel
Allocation
‘00’
CODEC 0 allocates on channel 0 of
ST-bus.
Accept power-up
setting
13
Codec Channel
Allocation
‘01’
CODEC 1 allocates on channel 1 of
ST-bus.
Should be set
14
Status Channel
Allocation
‘02’
Status allocates on channel 2 of STbus.
Should be set
15
General Mode
Control
‘00’
Select ST-bus, Microphone path
Enable.
Accept power-up
setting
16
System Clock
‘0D’
Select System Clock 4.096 MHz (as
well as ST-bus clock), PLL enable.
Should be set
17,18
Test Registers
-
Testing reserved for the
manufacturer.
-
19
Status Register
-
Read only.
-
0D-0F
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MSC8102ADSUM/D Ver. 1.2
User’s Manual
Functional Description
4.10 RS232 Transceivers
Two MSC8102ADS RS232 ports are connected to the following: the MSC8101 Host-side processor SCC1 port; and, the Slave-side UART port. The port connections assist in user applications
and, further, provide convenient communication channels for both the terminal and host computer.
Using a lone 3.3V single power supply with disable mode, the MAXIM MAX3241 Transceiver
internally generates RS232 levels during which receive buffers are tri-stated. When asserting (low)
the RS232_EN1 or RS232_EN2 bits in BCSR1/6-7, the corresponding transceiver is enabled.
When negated the receiver outputs are tri-stated and the corresponding transceiver is disabled.
For off-board applications it is possible to use Slave-side UART port signals via the J5 expansion
connector.
The 9-pin female D-Type RS232 connectors are configured to be directly connected (via a flat
cable) to a standard IBM-PC-like RS232 connector. Note the below figures, Figure 4-11 and
Figure 4-12, that illustrate the RS232 connector pinouts where the directions “I”, “O” are relative
to the MSC8102ADS board. For example, “I” means input to the MSC8102ADS.
The Host-side RS232 port provides expanded serial I/F including h/w flow control support.
The Slave-side UART port is intended for null-modem connectivity.
DTR
TXD
RXD
DSR
GND
1
2
6
7
8
9
3
4
5
DTR
CTS
RTS
NC
DB-9
Figure 4-11 Host RS232 Serial Port Connector
•
DTR - Data Terminal Ready. This line is always asserted by the MSC8102ADS. (O)
•
TXD - Transmit Data (O)
•
RXD - Receive Data (I)
•
DSR - Data Set Ready (I)
•
CTS - Clear To Send (I)
•
RTS - Request To Send (O)
1
RxDUART
2
TxDUART
3
GND
3-pin Header
Figure 4-12 Slave UART Serial Port Connector
•
RxDUART - Receive Data (I)
•
TxDUART - Transmit Data (O)
MSC8102ADSUM/D Ver. 1.2
User’s Manual
61
Functional Description
4.11 Packet Peripherals (Host-side)
4.11.1 ATM SONET Framer
MSC8101 ATM controller support is provided by an on-board 155.52 Mbps ATM Framer connected via UTOPIA-8 I/F to the FCC1 of the MSC8101. It is used in conjunction with PMC-Sierra’s
PM5384.
The Framer is controlled by the transceiver’s microprocessor I/F. The buffered microprocessor
I/F is configured by the MSC8101 memory controller in Memory Controller General Purpose Chipselect Machine (GPCM) mode. The Framer has a 3.3V power supply and connects directly to the
MSC8101’s CPM port.
ATM Framer reset input is driven by the MSC8101’s HRESET signal and, as such, reset occurs
whenever a Hard Reset sequence is performed. The ATM Framer may be reset by either asserting
ATM_RST bit in BCSR1/3 or by a sw controlled internal register.
ATM Framer transmit and receive clocks are fed by a 19.44 MHz +/- 20 ppm clock generator
powered by 3.3V power supply. MSC8101 provides the receive and transmit FIFO clock - either
from the same or a separate hard-configured clock.
The ATM SAR is connected by an optical I/F to the physical medium. HP’s HFBR 5805 optical
I/F, operating at 1300 nm with up to a 2 km transmission range, is used.
4.11.2 10/100 T-Base Ethernet Phy
A Fast Ethernet port with T.P. (100-Base-TX) I/F is provided on the MSC8102ADS. The port
also supports 10 Mbps Ethernet (10-Base-T) via the LSI LS80225 Transceiver.
LS80225 operates from a single 3.3V power supply and connects directly to the FCC2 port of
the MSC8101 via the MII interface. The interface is used for both device control and data path. The
initial LS80225 configuration is achieved by setting the MII control port to address “0”.
LS80225 reset input is driven by MSC8101’s HRESET signal. The transceiver is reset
whenever a Hard Reset sequence is undertaken. The Phy is able to interrupt the MSC8101 via the
IRQ7 line.
4.12 Board Control & Status Register - BCSR
The BCSR, an 8-bit wide read / write register file, controls or monitors most of the ADS
hardware options. For the full ADS board configuration the BCSR resides on the Host 60-x bus. In
the case of the ADSs board configuration, the BCSR is interfaced to the MSC8102’s System Bus.
The BCSR includes 6 registers, BCSR0 to BCSR5. The BCSR6 - BCSR7 slices are not implemented.
BCSR0 to BCSR6 are duplicated numerous times within a CS region. This is due to the CS
region’s 32KB minimum block size and the fact that only address lines A[29:31] are decoded for
register selection by the BCSR. BCSR is implemented on a PLD Altera device that provides
register and logic functions over some ADS signals. See Table 2-1 "MSC8102ADS Specifica-
62
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Functional Description
tions" on page 20.
The BCSR controls or monitors the following functions:
1)
Power-on-Reset configuration setting for the Slave-side.
2)
Hard Reset for Host and up to four Slaves (three of which are ADSs off-board Slaves).
3)
Soft Reset for Host and an on-board Slave.
4)
Hardware Reset for the following devices:
•
T1/E1 Framer FALC56
•
Fast Ethernet Phy
•
ATM Framer
•
TSI device
5)
RS232 (Host and Slave) Enable / Disable port.
6)
CODEC Enable and Reset device is found on the serial control port.
7)
BCSR provides FLASH (Host and Slave) devices with h/w boot protection.
8)
BCSR provides TDM port # 3 with muxing between the E1/T1 Framer and the TSI device.
9)
Two Host LEDs (one green, one red) provide s/w signaling.
10) Two Slave LEDs (one green, one red) provide s/w signaling.
11) Secondary Power-On-Reset Control for the MSC8102 exists.
12) ADS has special function support for MSC8102 (test functions register).
13) Status register includes:
•
Software Option Identification (set by DIP SW5 Switch)
•
ADS Configuration code
•
ADS Revision code
•
BCSR Revision code
Sections of the BCSR slice control registers generally have low active notations. This means
that a bit function will be realized while the bit is zero. When a bit is set to “1” a related function is
disabled. The default setting is assumed to be non-functional.
4.12.1 BCSR0 - Board Control / Status Register 0
The BCSR0 serves as a control register on the ADS and, although it only resides over D(0:7)
lines of the 60-x data bus, it is accessed from the BCSR base address as a byte at offset 0x0.
The BCSR0 may be read or written at any time. BCSR0 defaults are attributed at the time of main
Power-On-Reset or HRESETh. BCSR0 fields are described below in Table 4-9 "BCSR0 Description":
Table 4-9 BCSR0 Description
BIT
MNEMONIC
Function
DEF
ATT.
0
FLASHPRT1
Flash 1 h/w Protection. HCW and boot code, found in the Flash boot
sector, are protected in the Host-side Flash when the FLASHPRT1 is
asserted (low). To unprotect the Flash boot sector, reset unlock bit
FLUNLCK1 at BCSR6.0 and then write high in the FLASHPRT1 bit. This
allows for further erase/write operations in the boot sector.
0
R,W
MSC8102ADSUM/D Ver. 1.2
User’s Manual
63
Functional Description
Table 4-9 BCSR0 Description
BIT
MNEMONIC
1
FLASHPRT2
2
DEF
ATT.
Flash 2 h/w Protection. HCW and boot code, found in the Flash boot
sector, are protected in the Slave-side Flash when the FLASHPRT2 is
asserted (low). To unprotect the Flash boot sector, reset unlock bit
FLUNLCK2 at BCSR6.1 and then write high in the FLASHPRT2 bit. This
allows for further erase/write operations in the boot sector.
0
R,W
FRM_RST
E1/T1 Framer Reset. The FALC56 device is reset when the FRM_RST is
asserted (low). The HRESETh signal of the MSC8101 will assert the
FRM_RST signal.
1
R/W
3
CODEC_EN
CODEC Enable. The Mitel MT92303 CODEC chip is selected for the
serial control bus and is programmable when the CODEC_EN bit is
asserted (low). The CODEC device is disabled for programming purposes
when negated (high).
1
R,W
4
SIGNALS0
Signal LED Slave 0. A dedicated Green LED is illuminated when
SIGNALS0 is active (low). The LED is unlit when in its inactive (default)
state (high). During the Reset Configuration sequence the LED indicates
the state of Slave HRESETs assertion. The user may utilize the LED for s/w
Slave signalling purposes.
1
R,W
5
SIGNALS1
Signal LED Slave 1. A dedicated Red LED is illuminated when SIGNALS1
is active (low). The LED is unlit when in its inactive (default) state (high).
During the Reset Configuration sequence the LED indicates the state of
Slave SRESETs assertion. The user may utilize the LED for s/w Slave
signalling purposes.
1
R,W
6
SIGNALH0
Signal LED Host 0. A dedicated Green LED is illuminated when
SIGNALH0 is active (low). The LED is unlit when in its inactive (default)
state (high). During the Reset Configuration sequence the LED indicates
the state of Host HRESETh assertion. The user may utilize the LED for s/w
Host signalling purposes.
1
R,W
7
SIGNALH1
Signal LED Host 1.A dedicated Red LED is illuminated when SIGNALH1 is
active (low). The LED is unlit when in its inactive (default) state (high).
During the Reset Configuration sequence the LED indicates the state of
Host SRESETh assertion. The user may utilize the LED for s/w Host
signalling purposes.
1
R,W
Not Implemented.
-
-
8-31
-
Function
4.12.2 BCSR1 - Board Control / Status Register 1
On the ADS, the BCSR1 acts as a control register and is accessed from the BCSR base
address as a byte at offset 0x4. The BCSR1, which may be read or written at any time, receives
its defaults upon main Power-On-Reset or HRESET. The BCSR1 fields are described below in
Table 4-10 "BCSR1 Description":
Table 4-10 BCSR1 Description
BIT
0
64
MNEMONIC
RECONF
Function
Start Slave Re-configuration. Bit RECONF is associated with the Slave
PRSTs signal and, when set (low), enables performance of the Slave’s
secondary Power-on-Reset configuration. When negated (high) the bit
has no influence on the state of the board.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
DEF
ATT.
1
W
Functional Description
Table 4-10 BCSR1 Description
BIT
MNEMONIC
Function
DEF
ATT.
1
HRST1
Hard Reset to Slave1. The HRST1 signal is asserted to external off-board
Slave1 when bit HRST1 is set (low). When negated (high) the bit has no
influence on the state of the HRST1 signal. Reading the bit results in the
sampling of external off-board Slave1 and, as such, provides an indication
of the Slave processor’s state.
1
R,W
2
HRST2
Hard Reset to Slave2. The HRST2 signal is asserted to external off-board
Slave2 when bit HRST2 is set (low). When negated (high) the bit has no
influence on the state of the HRST2 signal. Reading the bit results in the
sampling of external off-board Slave2 and, as such, provides an indication
of the Slave processor’s state.
1
R,W
3
ATM_RST
ATM Peripheral Reset. Upon activation (low) the ATM port transceiver
enters into a reset state. The same applies to the ATM_RST signal when
the HRESETh signal of the MSC8101 is asserted.
1
R,W
4
HRST3
Hard Reset to Slave3. The HRST3 signal is asserted to external off-board
Slave3 when bit HRST3 is set (low). When negated (high) the bit has no
influence on the state of the HRST3 signal. Reading the bit results in the
sampling of external off-board Slave3 and, as such, provides an indication
of the Slave processor’s state.
1
R,W
5
FETH_RST
Fast Ethernet Peripheral Reset. Upon activation (low), the PHY LSI
80225 enters into a reset state and the MII port control bits revert to their
default values. The same applies to the FETH_RST signal when the
HRESETh signal of the MSC8101 is asserted.
1
R,W
6
RS232EN_1
RS232 Transceiver Host-side Enable. Upon activation (low), the RS232
Transceiver, using the SCC1 port of the Host MSC8101, is enabled. When
negated (high), the RS232 Transceiver enters standby mode.
1
R,W
7
RS232EN_2
UART Transceiver Slave-side Enable. Upon activation (low), the
MSC8102 UART port transceiver is enabled. When negated (high), the
RS232 Transceiver enters standby mode and the UART port pins become
available for off-board use (via the J5 expansion connectors).
1
R,W
Not Implemented.
-
-
8-31
-
4.12.3 BCSR2 - Board Control / Status Register 2
On the ADS, the BCSR2 serves as both a control register and a MSC8102 Slave configuration
setting. It is accessed from the BCSR base address as a byte at offset 0x8 and, it should be noted,
may be read or written at any time. Depending upon the Slave Configuration DIP Switch SW4/3
(SYS/DSI) setting, the BCSR2 receives its defaults upon main Power-On-Reset or HRESETh. The
BCSR2 fields are described below in Table 4-11 "BCSR2 Register Description":
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65
Functional Description
Table 4-11 BCSR2 Register Description
DEF AULT
BIT
MNEMONIC
Function
ATT.
SYS
0
RSTCNF
Reset Configuration Mode. During the Slave Power-on-Reset
configuration sequence the RSTCNF signal drives the logical level of the
bit’s value. The user may, at any time, change the value of bit RSTCNF.
DSI
R,W
0
1
CNFG
Configuration Source. During the Slave Power-on-Reset configuration
sequence the CNFG signal drives the logical level of the bit’s value. After
the sequence the signal enters the Hi-Z state. The user may, at any time,
change the value of bit CNFG.
0
1
R,W
2
SWTE
Software Watchdog Timer Enable. During the Slave Power-on-Reset
configuration sequence the SWTE signal drives the logical level of the bit’s
value. After the sequence the signal enters the Hi-Z state. After completing
the configuration process negation occurs (low) and the s/w watchdog timer
is disabled. If asserted (high) then the s/w watchdog timer is enabled.
1
0
R,W
3
DSI64
DSI /System 64/32 -bit. The DSI64 signal indicates DIP Switch SW7/3 and
is permanently set at the time of main Power-on-Reset. After the sequence
the signal enters the Hi-Z state. When negated (low) the DSI bus
configures to 32-bit and the System bus to 64-bit. If asserted (high) the DSI
bus configures to 64-bit and the System bus to 32-bit.
4
DSISYNC
5
HRST
6
R,W
DSI Synchronous Mode. During the Slave Power-on-Reset configuration
sequence the DSISYNC signal drives the logical level of the bit’s value.
After the sequence the signal enters the Hi-Z state. When negated (low) the
DSI bus configures to an asynchronous mode or, if asserted (high), to a
synchronous mode. The latter mode is not supported in MSC8101 Host.
0
R,W
1
Soft Reset to Slave. The HRESETs signal is asserted to the on-board
MSC8102 Slave when bit HRESETs is set (low). When negated (high) the
bit has no influence on the state of the HRESETs signal. Reading the bit
results in the sampling of the MSC8102 Slave and, as such, provides an
indication of the Slave processor’s state.
FRMtoTSI
8-31
-
Hard Reset to Slave. The HRESETs signal is asserted to the on-board
MSC8102 Slave when bit HRESETs is set (low). When negated (high) the
bit has no influence on the state of the HRESETs signal. Reading the bit
results in the sampling of the MSC8102 Slave and, as such, provides an
indication of the Slave processor’s state.
SRST
7
R
-
R,W
1
E1/T1 Framer to TSI device. The TDM channels of the FALC56 device are
connected to a TSI device when the FRM to TSI is asserted (low). When
the FRMtoTSI is negated (high) the TDM channels of the FALC56 device
are tied directly to a TDM3 port of the MSC8102. Both muxing instances
occur via a bus switch.
Not Implemented.
1
-
R,W
-
4.12.4 BCSR3 - Board Control / Status Register 3
On the ADS, the BCSR3 serves as both a control register and a Slave (MSC8102) configuration
setting. It is accessed from the BCSR base address as a byte at offset 0xc and, it should be noted,
may be read or written at any time. Depending upon the Slave Configuration DIP Switch SW4
66
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User’s Manual
-
Functional Description
setting, the BCSR3 receives its defaults upon main Power-On-Reset or HRESET. The BCSR3
fields are described below in Table 4-12 "ADS BCSR3 Register Description":
.
Table 4-12 ADS BCSR3 Register Description
DEF AULT
BIT
MNEMONIC
Function
ATT.
SYS
0-1
DSI
CLKMD[1:2]
Clock Mode Setting Bits 1-2 for Slave. During the Slave Poweron-Reset configuration sequence the CLKMD signals drive the
logical level of the bit’s value. After the sequence the signals enter
the Hi-Z state. The user may, at any time, change the value of bits
CLKMD[1:2].
From
DIP Switch
SW4/1-2
R,W
SEE0
Slave Emulation Enable 0. Bit SEE0 controls the Slave debug
request. When bit SEE0 is asserted (low) then PLD logic
generates a short positive pulse for the Slave EE0 input.
Consequently MSC8102 enters debug mode despite the DIP
Switch SW4/4 setting. Toggling the DIP Switch SW4/4 (DBG)
setting achieves the same results as those described above.
Reading bit SEE0 results in the sampling of the MSC8102 EE0
signal state.
Slave EE0
signal
R,W
3-4
Reserved
Not Implemented.
‘11’
R
5-7
BTMD[0:2]
Boot Mode Bits 0-2. During the Slave Power-on-Reset
configuration sequence the BTMD signals drive the logical level of
the bit’s value. After the sequence the signals enter the Hi-Z state.
The user may, at any time, change the value of bits BTMD[0:2]
‘000’
Not Implemented.
-
2
8-31
-
‘001’
R,W
-
-
Table 4-13 Summary Slave Configuration Modes
MSC8102 Config. Inputs
DSI/SYS
DIP
Switch
BM[0:2]
SWTE
RSTCNF
CNFGS
On
‘001’
0
0
1
Configuration & Boot performed through DSI
bus.
Off
‘000’
1
0
0
Configuration & Boot performed through
System bus when MSC8102 is a Boot Master.
Slave Configuration Description
4.12.5 BCSR4 - Board Status Register - 4
BCSR4 is a status register accessed from the BCSR base address as a byte at offset 0x10.
BCSR4 is a Read-Only register that may be read at any time. The BCSR4 fields are described
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User’s Manual
67
Functional Description
below in Table
4-14 "BCSR4 Description":
Table 4-14 BCSR4 Description
DEF
SET
ATT.
-
R
SW5/1-3
DIP
Switch
R
Not Implemented.
‘111’
R
Not Implemented.
-
-
BIT
MNEMONIC
0-1
SEE[0:1]
Slave Emulation Enable Bits 0-1. Bits SEE[0:1] illustrate the state
of the Slave’s EE0 and EE1 lines.
2-4
SWOPT[0:2]
Software Option 0-2. Bits SWOPT[0:2] illustrate the state of
dedicated DIP Switch SW5/1-3. This DIP Switch provides the option
for manually changing a program’s flow.
5-7
Reserved
8-31
-
Function
4.12.6 BCSR5 - Board Identification Register - 5
BCSR5 is a Read-Only register accessed from the BCSR base address as a byte at offset
0x14. The BCSR5 fields are described below in Table 4-15 "BCSR5 Description":
Table 4-15 BCSR5 Description
BIT
MNEMONIC
Function
ATT.
0-1
BCONF[0:1]
Board Configuration Type. Field BCONF[0:1] represents the ADS
configuration type. See Table 4-16 "ADS Configuration Encoding"
for ADS configuration encoding.
R
2-4
BREVN[0:2]
Board Revision Number 0-2. Field BREVN[0:2] represents the ADS
revision code. See Table 4-17 "ADS Revision Encoding" for revised
ADS encoding.
R
5-7
BCSRREV[0:2]
BCSR Revision Number 0-2. Field BCSRREV[0:2] represents the revised
BCSR code. See Table 4-18 "BCSR Revision Encoding" for revised
BCSR encoding.
R
8-31
-
Not Implemented.
-
Table 4-16 ADS Configuration Encoding
Configuration Code[0:1]
ADS Configuration
0
ADS - the complete ADS includes both the
MSC8101and MSC8102 processors
1
ADSs - the single ADS includes only the
MSC8102 processor
2-3
Reserved
Table 4-17 ADS Revision Encoding
68
Revision Number [0:2]
ADS Revision
0
PROTO
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Functional Description
Table 4-17 ADS Revision Encoding
Revision Number [0:2]
ADS Revision
1
PILOT
2
A
3-7
Reserved
Table 4-18 BCSR Revision Encoding
Revision Number [0:2]
BCSR Revision
0-7
1.x - 8.x
4.12.7 BCSR6 - Board Miscellaneous Register - 6
BCSR6 is a service register accessed from the BCSR base address as a byte at offset 0x16.
The BCSR6 fields are described below in Table 4-19 "BCSR6 Description".
Table 4-19 BCSR6 Description
BIT
MNEMONIC
Function
DEF
ATT.
0
FLUNLCK1
Flash 1 Protection Unlock. The default for hardware write protection bit
FLUNLCK1 is negation (high) and consequently bit BCSR0.0 FLASHPRT1
is locked. In order to unlock bit BCSR0.0 FLASHPRT1 then bit FLUNLCK1
must be asserted (low).
1
R,W
1
FLUNLCK2
Flash 2 Protection Unlock. The default for hardware write protection bit
FLUNLCK2 is negation (high) and consequently bit BCSR0.1 FLASHPRT2
is locked. In order to unlock bit BCSR0.1 FLASHPRT2 then bit FLUNLCK2
must be asserted (low).
1
R,W
2-6
Reserved
Not Implemented.
1
-
7
Reserved
Not Implemented.
0
-
Not Implemented.
-
-
8-31
-
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Functional Description
70
MSC8102ADSUM/D Ver. 1.2
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Support Info
Section 5 Support Info
5.1 Memory Map
5.1.1 Host 60-x Bus Mapping
The MSC8101 Memory Controller governs all access to the MSC8101 memory slaves. Consequently the memory map may be reprogrammed according to user needs. After performing Hard
Reset, the debug host may initialize the memory controller via the P14 connector at the JTAG/
OnCE port as this allows additional access to bus addressable peripherals. The SDRAM and
FLASH memory respond to all types of memory access - program/data and Direct Memory Access
(DMA).
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Support Info
Table 5-1 Host MSC8101 Memory Map
ADDESS RANGE
Memory Type
Device Name
00000000 - 0007FFFF
Internal SRAMa
00080000 - 00EFFDFF
Empty Space
00EFFE00 - 00EFFEFF
EOnCE Registersa
00EFFF00 - 00EFFFFF
Empty Space
00F00000 - 00F0FFFF
DSP Peripherals (Qbus Bank0)
00F10000 - 00F7FFFF
Empty Space
00F80000 - 00F807FF
Boot ROM (Qbus Bank1)
00F80800 - 01EFFFF
Empty Space
01F00000 - 01F0FFFF
DSP Peripherals (CS11)
01F10000 - 01FFFFFF
Empty Space
02000000 - 0207FFFF
Internal SRAM (CS10)
02080000 - 144FFFFF
Empty Space
14500000 - 14507FFF
BCSR(0:5):
14500000
MSC8101 Internal Space
14500004
BCSR1
14500008
BCSR2
1450000C
BCSR3
ALTERA EPM3256
resides on 60-x Bus
32Kb
8
-
-
32Kc
8
-
-
128K
32
-
-
16M
64
-
-
BCSR4
14500014
BCSR5
14500018
BCSR6
14508000 - 145FFFFF
Empty Space
14600000 - 14607FFF
ATM SONET
Control
14608000 - 146FFFFF
Empty Space
14700000d - 1483FFFF
MSC8101 60-x Bus Memory and
CPMe
14840000 - 1FFFFFFF
Empty Space
20000000 - 20FFFFFF
SDRAM
21000000 - 23FFFFFF
Empty Space
72
Port Size
in Bit
64
BCSR0
14500010
Volume
in Byte
Framer
Proc.
PM5384
MSC8101 Internal Space
MT48LC2M32B2 x 2
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
Table 5-1 Host MSC8101 Memory Map
ADDESS RANGE
Memory Type
Device Name
Volume
in Byte
Port Size
in Bit
24000000 - 241FFFFF
Slave0 (off-board) DSI Bus
MSC8102 ID 0
2M
32/64f
25E00000 - 25FFFFFF
Slave15 (on-board) DSI Bus
MSC8102 ID 15
2M
32/64f
26000000 - 261FFFFF
Broadcast Access over DSI Bus
All MSC8102
2M
32/64f
26200000 - FFBFFFFF
Empty Space
-
-
FFC00000 - FFFFFFFF
Flash
4M
16
Am29LV320
a. The internal SDRAM is mapped to fixed addresses in the SC140 core. Refer to the MSC8101 spec for a
complete description of the SC140 Core internal memory map. [2].
b. The 32KB device appears repeatedly in port-size (byte) x depth multiples. For example, BCSR0 appears
at memory locations 14700000, 14700010, 14700020..., while BCSR1 features at 14700004, 14700014,
14700024... and so on.
c. The internal space of the ATM SONET Framer control port is 256 bytes, however, the minimum block size
controllable by a CS region is 32KB. The same logic applies to other peripherals.
d. After the Hard Reset configuration sequence is finished then MSC8101 internal registers are automatically
placed in the hF0000000 - hF000FFFF address area. Following this the Host debugger tool initializes a reconfigured memory space as shown in Table 5-1 "Host MSC8101 Memory Map".
e. The MSC8101 spec comprehensively describes the MSC8101 Internal Memory Map.
f. The DSI port size is dependant upon the MSC8102 Power-on-Reset configuration pin.
The memory map defined in Table 5-1 "Host MSC8101 Memory Map" is only a recommendation for the user can choose to work with alternative memory mapping. It should be noted that
the described mode is supported by Metrowerks’ CodeWarrior debug tool.
5.1.2 Slave System Bus Mapping
The MSC8102 Memory Controller governs all access to the MSC8101 memory slaves. Consequently the memory map may be reprogrammed according to user needs. After performing Hard
Reset, the debug host may initialize the memory controller via connectors P14 or P15 at the JTAG/
OnCE port for this allows additional access to bus addressable peripherals. SDRAM and FLASHmemory respond to all types of memory access - program / data and DMA.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
73
Support Info
.
Table 5-2 Slave MSC8102 Memory Map
ADDRESS RANGE
Memory Type
Device Name
Config
Volume
in Byte
Port
Size
in
Bit
224K
64
00000000 - 00037FFF
L1 Memory on Internal Busa
00038000 - 00EFFDFF
Empty Space
00EFFE00 - 00EFFFFF
EOnCE
00F00000 - 00F0FFFF
DSP Peripherals (Qbus Bank0)
00F10000 - 00FFFFFF
Empty Space
01000000 - 01076FFF
L2 Memory (MQbus)
01077000 - 01077FFF
Boot ROM (MQbus)
01078000 - 017FFFFF
Empty Space
01800000 - 01FFFFF
SQbus Internal Space
02000000 - 02076FFF
L2 Memory (System bus)
02077000 - 02077FFF
Boot ROM (System bus)
02080000 - 020B7FFF
L1MEM0 (System bus)
020C0000 - 020F7FFF
L1MEM1 (System bus)
02100000 - 02137FFF
L1MEM2 (System bus)
02140000 - 02177FFF
L1MEM3 (System bus)
02178000 -0217FFFF
Empty Space
02180000 - 021BFFFF
CS9 - (IP address space)
021E0000 - 021FFFFF
CS10 - (EFCOP,FDIR, FDOR)
02200000 -145FFFFF
Empty Space
14600000 - 14607FFF
Time-Slot-Interchanger (TSI)
PEF24471
32Kb
8
14608000 - 1460FFFF
FALC56 E1/T1 Framer
PEB2256
32Kc
8
14610000 - 146FFFFF
Empty Space
-
-
-
14700000d - 14713FFF
MSC8102 System I/F
-
128K
32
14820000 - 1FFFFFFF
Empty Space
-
-
-
20000000 - 20FFFFFF
OR
20000000 - 208FFFFF
64-bit SysBus
16M
64
SDRAM
32-bit SysBus
8M
32
-
-
4M
8
480 KB
MSC8102
Internal Space
Any
480 KB
224 KB
x4
MSC8102
Internal Space
MT48LC2M32B
2x2
MT48LC2M32B
2x1
22000000 - FFBFFFFF
Empty Space
FFC00000 - FFFFFFFF
Flash
74
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MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
a. L1 Memory is mapped to fixed addresses in the SC140 core. See the MSC8102 spec for a complete description of the SC140 Core internal memory map [1].
b. The TSI device’s internal space is 32 bytes, however, the minimum block size controllable by a CS region
is 32KB.
c. The E1/T1 FALC56 Framer device’s internal space is 256 bytes, however, the minimum block size controllable by a CS region is 32KB.
d. After the Hard Reset configuration sequence is finished then MSC8101 internal registers are automatically
placed in the hF0000000 - hF000FFFF address area. Following this the Host debugger tool initializes a reconfigured memory space as shown in Table 5-2 "Slave MSC8102 Memory Map"
MSC8102ADSUM/D Ver. 1.2
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75
Support Info
5.2 Host Memory Controller Registers’ Programming
The MSC8101 Memory Controller in the MSC8102ADS is initialized for an 100/66 MHz bus operation. For example, programming of the registers is based on a 100/66 MHz timing calculation.
Warning
Initializations noted in Table 5-3 "Host’s Memory Controller Initialization for 100(66) MHz"
below are based on ADS board design.
Table 5-3 Host’s Memory Controller Initialization for 100(66)a MHz
Reg.
Device Type
Buffered
60-x
BR0
OR0
Init Value
[hex]
Bus
Am29LV320 by AMD
BR1
OR1
BCSR0-6 Implemented in
Altera EPM3256
BR2
SDRAM 64-bit Supported
OR2
SDRAM
MT48LC2M32B2T6-8x2 by
Micron
BR3
MSC8102 DSI Port broadcast CS
OR3
BR4
MSC8102 DSI Port
Buffered
60-x
Non-buffered
60-x
Non-buffered
60-x
Non-buffered
60-x
OR4
BR6
PM5384 - ATM UNI
User’s peripheral
OR6
BR10
DSPRAM
OR10
BR11
OR11
76
DSP Peripherals
Buffered
60-x
Buffered
PPC
Base at FFC0_0000, 16-bit port size, no parity, GPCM.
FFC00874
(FFC00854)
4MB block size, CS early negate, 14(10) w.s., Timing
relax.
14501801
Base at 14500_000, 32-bit port size, no parity, GPCM.
FFFF8820
(FFFF8810)
32 KB block size, all types access, CSNT=1,
2 w.s.
(32 KB block size, all types access, CSNT=1,
1 w.s.)
20000041
Base at 2000_0000, 64-bit port size, no parity, SDRAM
machine 1.
FF003080
16MB block size, 4 banks per device, row starts at A8, 11
row lines, internal bank interleaving allowed.
26001801
Base at 2800_0000, 32-bit port size, no parity, GPCM.
26000001
Base at 2800_0000, 64-bit port size, no parity, GPCM.
FFE00844
(FFE00884)
2MB block size, CSNT, four/eight wait states, TRLX.
24001881
Slave’s based at 2400_0000 (on-Board Slave based at
2600_0000), 32-bit port size, no parity, UPMA.
24000081
Slave’s based at 2400_0000 (on-Board Slave based at
2600_0000), 64-bit port size, no parity, UPMA.
FE000100
(FE000100)
BR5
OR5
FFC01001
Description
32MB block size, non-burst.
146008A1
Base at 1460_0000, 8-bit port size, UPMB.
FFFF8100
32KB block size, non-burst.
-
-
-
-
Local
PPC
020000C1
Base at 0020_0000, 64-bit port size, no parity, UPMC.
FFF80000
512KB block size.
Local
PPC
01F00021
Base at 01F0_0000, 64-bit port size, no parity, GPCM on
local PPC bus.
FFFF0000
64KB block size
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
Table 5-3 Host’s Memory Controller Initialization for 100(66)a MHz
Reg.
Device Type
PSDMR
SDRAM 64-bit
PSRT
SDRAM Supported
Init Value
[hex]
Bus
Non-buffered
PPC
C26B36A7
(C2692452)
Page interleaving, refresh enabled, normal operation,
address muxing mode SDAM=2, A(15-17) on BNKSEL(0:2), A8 on PSDA10, 8(4) clocks refresh recovery,
3(2) clocks precharge to activate delay, 3(2) clocks activate to read/write delay, 4 beat burst length, 2(1) clock
last data out to precharge, 2(1) clock write recovery time,
internal address muxing, normal timing, buffered (nonbuffered), 3(2) clocks CAS latency.
13
Generates refresh every 14 µsec instead of the outside
limit of every 15.6 µsec. Thus the refresh redundancy is
6.6 msec. The full SDRAM refresh cycle needs 64 msec.
For example, application s/w may withhold the 60x bus for
up to approx.
6.6 msec in a 57.3 msec period without jeopardizing the
contents of the 60x bus SDRAM.
All PPC
Bus
Config.
MPTPR
SDRAM Supported
Description
2800(1300)
Divide Bus clock by 40D (20D)
a. Table values marked with parentheses are indicative of the lower 66 MHz frequency bus.
-
Table 5-4 MAMR Programming (CS4:DSI)
Single Read
Single Write
Step
Register Name
Value to write
Description
MAMR
0x10048898
The noted value allows an array write operation to
control the write routine; UPMWAIT enabled; read/
write loop performed twice.
MDR
0x0FFFCC00
CS active & GPL2 are active
MDR
0x0CFFCC00
BS active, WAEN enable
MDR
0x00FFDD00
BS active, WAEN disable, begin loop
MDR
0x0FFFCC04
BS active, end loop
MDR
0x0FFFCF00
MDR
0x0FFFCC01
End access
MAMR
0x10C48880
The noted value allows an array write operation to
control the read routine; UPMWAIT enabled; read/
write loop performed twice.
MDR
0x0FFFCC00
Only CS active
MDR
0x0FFECC00
BS active, WAEN enable
MDR
0x0FFCDD00
BS active, WAEN disable, begin loop
MDR
0x0FFCCC04
BS active, end loop
MDR
0x0FFFCF00
CS negated, end access
MDR
0x0FFFCC01
CS negated, end access
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Support Info
Table 5-4 MAMR Programming (CS4:DSI)
Exception
Step
Run
Register Name
Value to write
Description
MAMR
0x10C488BC
The noted value allows an array write operation to
control the exception routine; UPMWAIT enabled;
read/write loop performed twice.
MDR
0xFFFFCC05
Access termination
MAMR
0x00C48880
Normal operation
Table 5-5 MBMR Programming (CS5:ATM)
Exception
Single Read
Single Write
Set
Run
78
Register Name
Value to write
Description
MBMR
0x10011018
The noted value allows an array write operation to
control the write routine; read/write loop performed
four times.
MDR
0x0FFFFC00
CS active is active
MDR
0x00FFFC80
BS active, begin loop
MDR
0x00FFFC80
BS active, end loop
MDR
0xFFFFFC00
CS negated & BS negated
MDR
0xFFFFFF05
End access
MBMR
0x10011000
The noted value allows an array write operation to
control the read routine; read/write loop performed
seven times.
MDR
0x0FFFFC00
CS active
MDR
0x0FFCFC80
GPL2 active, begin loop
MDR
0x00FCFC80
GPL2 active, end loop
MDR
0x0FFCFC04
GPL2 active, PSDVAL asserted
MDR
0x00FFFD00
MDR
0xFFFFFF01
End access
MBMR
0x1001103C
The noted value allows an array write operation to
control the exception routine.
MDR
0xFFFFCC05
MBMR
0x00011000
Normal operation
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
5.3 Slave Memory Controller Registers’ Programming
The MSC8102 Memory Controller in the MSC8102ADS is initialized for an 100/66 MHz bus operation. For example, programming of the registers is based on a 100/66 MHz timing calculation.
Warning
Initializations noted in Table 5-6 "Slave’s Memory Controller Initialization for 100(66) MHz"
below are based on ADS board design.
Table 5-6 Slave’s Memory Controller Initialization for 100(66)a MHz
Reg.
Device Type
Init Value
[hex]
Bus
Buffered
System Bus
BR0
OR0
Am29LV320 by AMD
BR1
NC
-
OR1
BR2
SDRAM 64-bit Supported
OR2
SDRAM
MT48LC2M32B2T68x2 by Micron
BR2
SDRAM 32-bit Supported
OR2
MT48LC2M32B2T6-8
by Micron
Non-buffered
System Bus
Non-buffered
System 32-bit
configuration
BR3
OR3
CS5CS7
Base at FFC0_0000, 8-bit port size, no parity, GPCM.
FFC00874
(FFC00854)
4MB block size, CS early negate, 14(10) w.s., Timing
relax.
-
-
-
-
20000041
Base at 2000_0000, 64-bit port size, no parity, SDRAM
machine 1.
FF0030a0
16MB block size, 4 banks per device, row starts at A8, 11
row lines, internal bank interleaving allowed.
20001841
Base at 2000_0000, 32-bit port size, no parity, SDRAM
machine 1.
FF8032a0
8MB block size, 4 banks per device, row starts at A9, 11
row lines, internal bank interleaving allowed.
14600881
Base at 1460_0000, 8-bit port size, no parity, UPMA.
FFFF8100
32 KB block size, non-burst.
Buffered
System Bus
14680881
Base at 1468_0000, 8-bit port size, no parity, UPMA.
E1/T1 FALC
Buffered
System Bus
FFFF8100
32 KB block size, non-burst.
Not used
-
-
Internal
System Bus
02181821
IP Bus
Base at 218_0000, 32-bit port size, no parity, GPCM
local bus.
FFFC0008
256KB block size, non-burst.
021E0021
Base at 21E0_0000, 64-bit port size, no parity, GPCM
local bus
FFFF0000
64 KB block size, non-burst
020000C1
Base at 2000_0000, 64-bit port size, no parity, UPMC
FFE00000
2M block size, non-burst.
BR9
OR9
BR10
EFCOP
Internal
System Bus
OR10
BR11
OR11
FFC00801
TSI
BR4
OR4
Description
L1’s & L2
Internal
System Bus
User define
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Table 5-6 Slave’s Memory Controller Initialization for 100(66)a MHz
Init Value
[hex]
Device Type
PSDMR
SDRAM 64-bit
Non-buffered
System Bus
C26B36A7
(C2692452)
Page interleaving, refresh enabled, normal operation,
address muxing mode SDAM=2, A(15-17) on BNKSEL(0:2), A8 on PSDA10, 8(4) clocks refresh recovery,
3(2) clocks precharge to activate delay, 3(2) clocks activate to read/write delay, 4 beat burst length, 2(1) clock
last data out to precharge, 2(1) clock write recovery time,
Internal address muxing, normal timing, 3(2) clocks CAS
latency.
SDRAM 32-bit
Non-buffered
System Bus
C28737A7
(C2432552)
Page interleaving, refresh enabled, normal operation,
address muxing mode 1, A(13-15) on BNKSEL(0:2), A9
on PSDA10, 8(4) clocks refresh recovery, 3(2) clocks
precharge to activate delay, 3(2) clocks activate to read/
write delay, 8 beat burst length, 2(1) clock last data out to
precharge, 2(1) clock write recovery time, Internal
address muxing, normal timing, 3(2) clocks CAS latency.
13
Generates refresh every 14 µsec instead of the outside
limit of every 15.6 µsec. Thus the refresh redundancy is
6.6 msec. The full SDRAM refresh cycle needs 64 msec.
For example, application s/w may withhold the System
bus for up to approx.
6.6 msec in a 57.3 msec period without jeopardizing the
contents of the System bus SDRAM.
PSRT
Bus
Description
Reg.
SDRAM Supported
All System
Bus
Config.
MPTPR
SDRAM Supported
2800(1300)
Divide Bus clock by 40D (20D).
a. Table values marked with parentheses are indicative of the lower 66MHz frequency bus.
Table 5-7 MAMR Programming (CS3:TSI & CS4:E1/T1 FALC)
Single Write
Step
80
Register Name
Value to write
[hex]
MAMR
10015418
The noted value allows an array write operation to control the write
routine; read/write loop performed five times.
MDR
FFFFFD00
Address setup
MDR
0FFFFC00
CS active
MDR
0FF33C80
GPL1(WR TSI) & GPL3(WR FALC) low, start loop
MDR
0FF33C80
GPL1(WR TSI) & GPL3(WR FALC) low, stop loop
MDR
0FFFFC00
GPL1(WR TSI) & GPL3(WR FALC) high
MDR
3FFFFC05
PSDVAL asserted, end access
Description
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
Table 5-7 MAMR Programming (CS3:TSI & CS4:E1/T1 FALC)
Exception
Single Read
Step
Run
Register Name
Value to write
[hex]
MAMR
10015400
The noted value allows an array write operation to control the read
routine; read/write loop performed five times.
MDR
FFFFFD00
Address setup
MDR
0F0CFC80
CS active, GPL0(RD TSI) & GPL2(RD FALC) low, stop loop
MDR
0F0CFC04
CS active, GPL0(RD TSI) & GPL2(RD FALC) low, PSDVAL
asserted
MDR
FFFFFC00
CS negated, GPL0(RD TSI) & GPL2(RD FALC) high
MDR
FFFFFD00
Double idle cycle
MDR
FFFFFC01
End access
MAMR
1001543C
The noted value allows an array write operation to control the read
routine.
MDR
FFFFCC05
Access termination
MAMR
00015400
Normal operation
Description
Table 5-8 MCMR Programming (CS9:L1s & L2 Memory)
Single Read
Burst Write
Single Write
Step
Register Name
Value to write
[hex]
MCMR
90051258
The noted value allows an array write operation to control the write
routine; read/write loop performed four times
MDR
00000040
Exception enable
MDR
00000045
Access termination
MCMR
90051260
The noted value allows an array write operation to control the burst
write routine; read/write loop performed four times.
MDR
00000C48
Increment address
MDR
00000C4C
Increment address with PSDVAL assertion - first beat
MDR
00000C4C
Increment address with PSDVAL assertion- second beat
MDR
00000044
PSDVAL assertion - third beat
MDR
00000045
PSDVAL assertion - fourth beat with access termination
MCMR
90051240
The noted value allows an array write operation to control the read
routine; read/write loop performed four times.
MDR
00030040
GPL2 is high, exception enable
MDR
00030045
GPL2 is high, access termination
Description
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User’s Manual
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Support Info
Exception
Burst Read
Step
Run
82
Register Name
Value to write
[hex]
MCMR
90051248
The noted value allows an array write operation to control the burst
read routine; read/write loop performed four times.
MDR
00030C48
GPL2 is high, increment address
MDR
00030C4C
GPL2 is high, increment address with PSDVAL assertion - first beat
MDR
00030C4C
GPL2 is high, increment address with PSDVAL assertion -second
beat
MDR
00030044
GPL2 is high with PSDVAL assertion -third beat
MDR
00030045
GPL2 is high, PSDVAL assertion - fourth beat with access termination
MCMR
9005127C
The noted value allows an array write operation to control the
exception routine.
MDR
FF000001
Access termination
MCMR
80011240
Normal operation
Description
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
5.4 Power
5.4.1 Power Supplies
There are three power buses:
1)
3.3V for the on-board Logic and I/O of two processors.
2)
1.5V for the Host MSC8101 Core and PLL.
3
1.5V for the Slave MSC8102 Core and PLL.
Both processor PLL’s will obtain filtering voltage from their Core power supply.
The main 3.3V supply is a high-performance DC-to-DC converter that provides up to a 4A
current for on and off -board loads. In addition are the two regular 1.5V linear voltage regulators
that produce quiet voltage for the processors. A suppressor Diode protects the board from the application of reverse voltage.
P1/P2
3V3
DC-to-DC
1.5V
1V5h
4A
1.5V
3.3V
1V5s
3V3IOh
12V
+3.3V
+5V
VCCSYN VCCSYN1 QVCC NVCC
Chassis
Power Supply
MSC8101
3.3V
5V
3V3IOs
J4/J5
VCCSYN
QVCC
Expansion Con.
Fuse
Expansion Con.
ADS Logic & Peripherals
NVCC
MSC8102
Figure 5-1 ADS Power Scheme
To support off-board application development, a 3.3V power bus is connected to expansion con-
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User’s Manual
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Support Info
nectors J1/J2. In this way external logic, mounted on a prototype board, may be powered directly
from the main ADS. It is strongly recommended that off-board cases with high current consumption.
5.5 Interconnect Signals
The MSC8102ADS interconnects with external devices via the following set of connectors:
1)
P1,P5 - 3.5mm Stereo Phone Jack
2)
P2 - RF SMB Socket
3)
P3, P4, P7, P9, P11, P12, P16, P18 to P22 - 11 Logic Analyzer MICTOR Connectors
4)
P6 - RJ45 for E1/T1 port
5)
P8 - D-type9 900 Female RS232 Port
6)
P10 - Three pins header for Slave’s UART Port
7)
P13 - PLD Altera’s In System Programming (ISP)
8)
P14 - Host JTAG/ONCE
9)
P15 - Slave JTAG/ONCE
10) P17 - Two pins header for EE1 MSC8102 debug request chain
11) P20 - RJ45 100/10 - Base-T Ethernet port
12) P23 - Power Supply
13) J1-J5 - Expansion Connectors
5.5.1 P1,P5 - Stereo Phone Jack Connectors
These are stereo 5-pin headphone connector with pinout as shown in Table 5-9 "P1,P5 - Stereo
Phone Connectors Interconnect Signals" below
Table 5-9 P1,P5 - Stereo Phone Connectors Interconnect Signals
Pin
No.
Signal Name
Description
1
COMMON
Analog Ground. Connect to AGND1 plane.
2
LEFT
Left channel
3
RIGHT
Right channel
10
SPEAKER LEFT
Not connected
11
SPEAKER RIGHT
Not connected
5.5.2 P2 - SMB Connector
RF Subminiature Coaxial Connector P2 is intended for an external clock source for MSC8102
when jumper JP4/2-3 is close.
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5.5.3 Logic Analyzer Connectors
There are P3, P4, P7, P9, P11, P12, P16, P18 to P22 - 38 pin, SMT, high density, matched
impedance connector made by AMP used for Logic Analyzer measurament. They contain all
MSC8101 signals unbuffered. The pinout of these connectors is shown in MSC8102ADS Schematics.
5.5.4 P6 - RJ45 E1/T1 Line Connector
The E1/T1 connector is Twisted-Pair compatible connector. It is implemented with a 90o, 8-pin,
RJ45 connector, signals of which are described in Table 5-10 "P6 - E1/T1 Line Connector In-
terconnect Signals" below
Table 5-10 P6 - E1/T1 Line Connector Interconnect Signals
Pin
No.
Signal Name
Description
1
RX1+
Twisted-Pair Receive Data positive input from the MSC8102ADS.
2
RX1-
Twisted-Pair Transmit Data positive input from the MSC8102ADS.
3
GND
Digital Ground plane.
4
TX1+
Twisted-Pair Transmit Data positive output from the MSC8102ADS.
5
TX1-
Twisted-Pair Transmit Data negative output from the MSC8102ADS.
6
GND
Digital Ground plane.
7
N.C.
Not Connected.
8
5.5.5 P10 - Slave UART Port Connector
The RS232 port connector - P10 is 9 pin, 90o, female D-Type shielded connector, signals of which
are presented in Table 5-11 "P10 Interconnect Signals"
Table 5-11 P10 Interconnect Signalsa
Pin No.
Signal Name
Description
1,6
DTR
Data Terminal Ready output from the MSC8102ADS shorted to pin 1.
2
TXD
Transmit Data output from the MSC8102ADS.
3
RXD
Receive Data input to the MSC8102ADS.
4
DSR
Data Set Ready input to the MSC8102ADS.
5
GND
Ground signal of the MSC8102ADS.
7
CTS
Clear To Send input to the MSC8102ADS.
8
RTS
Ready To Send output from the MSC8102ADS.
9
N.C.
Not connected
a. Refer to Figure
4-12 "Slave UART Serial Port Connector" on page 61.
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Support Info
5.5.6 P13 - Altera’s In System Programming (ISP)
This is a 10 pin generic 0.100" pitch header connector, providing In System Programming capability for Altera CPLD devices made programmable logic on board. The pinout of P13 is shown in
Table 5-12 "P13 - ISP Connector - Interconnect Signals" below:
Table 5-12 P13 - ISP Connector - Interconnect Signals
Pin No.
Signal Name
Attribute
Description
1
TCK
I
ISP Test port Clock. This clock shifts in / out data to / from the programmable logic JTAG chain.
2
GND
P
Digital GND. Main GND plane.
3
TDO
O
ISP Transmit Data Output. This the prog. logic’s JTAG serial data output
driven by Falling edge of TCK.
4
VCC
P
Connect to 3.3V power supply bus for feeding an external programmer
logic.
5
TMS
I
ISP Test Mode Select. This signal qualified with TCK, changes the state of
the prog. logic JTAG machine.
6
N.C.
-
Not Connected.
7
N.C.
-
Not Connected.
8
N.C.
-
Not Connected.
9
TDI
I
ISP Transmit Data In. This is the prog. logic’s JTAG serial data input..
10
GND
P
Digital GND. Main GND plane.
5.5.7 P14 - Host Debug OnCE (SYS) Connector
P14 is a Motorola standard JTAG/ONCE connector for the DSP. It is a 14 pin 90o two row header
connector with key. Host debug may access through connector P14 to all processors joned by
JTAG chain. The pinout of P14 is shown in Table 5-13 "P14 - Main ONCE Connector - Inter-
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Support Info
connect Signals" below:
Table 5-13 P14 - Main ONCE Connector - Interconnect Signals
Pin No.
Signal Name
Attribute
Description
1
TDIh
I
Transmit Data In. This is the JTAG serial data input of the MSC8101, sampled on the rising edge of TCK.
2
GND
P
Digital GND. Main GND plane.
3
TDOhc
O
Transmit Data Output. This the DSP JTAG serial data output driven by
Falling edge of TCK.
4
GND
P
Digital GND. Main GND plane.
5
TCKhc
I
Test port Clock. This clock shifts in / out data to / from the JTAG logic.
Data is driven on the falling edge of TCK and is sampled both internally
and externally on it’s rising edge.
6
GND
P
Digital GND. Main GND plane.
7
N.C.
-
Not Connected.
8
KEY
-
No pin in connector. Serve for correct plug insertion.
9
HRESEThb
I/O,P.U.
When asserted by an external H/W, generates Hard-Reset sequence for
the MSC8101. During that sequence, asserted by the MSC8101 for 512
system clocks. Pulled Up on the ADS using a 1KΩ resistor.
When driven by an external tool, MUST be driven with an Open Drain
gate. Failure to do so might result in permanent damage to the
MSC8101 and / or to ADS logic.
10
TMSh
I
Test Mode Select. This signal qualified with TCK in a same manner as
TDI, changes the state of the JTAG machines. This line is pulled up internally by the MSC8101.
11
VDD
P
Connect to 3.3V power supply bus via protection resistor. May be used for
Command Convertor power.
12
N.C.
-
Not Connected.
TRSThb
I
Test port Reset. When this signal is active (Low), it resets the JTAG logic.
This line is pull-down on the ADS with a 2.2KΩ resistor, to provide continuous reset of the JTAG logic, when connector is unplugged.
13
14
13
P14
14
1
2
Figure 5-2 P14 connector front view
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Support Info
5.5.8 P15 - Slave Debug OnCE (SLV) Connector
P15 is a Motorola standard JTAG/ONCE connector for the DSP. It is a 14 pin straight two row
header connector with key. Host debug may access through connector P15 to MSC8102 when
separate JTAG chain mode is chosen by DIP SW7/1,2 switch. The pinout of P15 is shown in Table
5-14 "P15 - Slave ONCE Connector - Interconnect Signals" below:
Table 5-14 P15 - Slave ONCE Connector - Interconnect Signals
Pin No.
Signal Name
Attribute
Description
1
TDIsc
I
Transmit Data In. This is the JTAG serial data input of the MSC8102, sampled on the rising edge of TCK.
2
GND
P
Digital GND. Main GND plane.
3
TDOsc
O
Transmit Data Output. This the MSC8102’s JTAG serial data output driven
by Falling edge of TCK.
4
GND
P
Digital GND. Main GND plane.
5
TCKsc
I
Test port Clock. This clock shifts in / out data to / from the JTAG logic.
Data is driven on the falling edge of TCK and is sampled both internally
and externally on it’s rising edge.
6
GND
P
Digital GND. Main GND plane.
7
N.C.
-
Not Connected.
8
KEY
-
No pin in connector. Serve for correct plug insertion.
9
HRESETsb
I/O,P.U.
When asserted by an external H/W, generates Hard-Reset sequence for
the MSC8102. During that sequence, asserted by the MSC8102 for 512
system clocks. Pulled Up on the ADS using a 1KΩ resistor.
When driven by an external tool, MUST be driven with an Open Drain
gate. Failure to do so might result in permanent damage to the
MSC8102 and / or to ADS logic.
10
TMSsc
I
Test Mode Select. This signal qualified with TCK in a same manner as
TDI, changes the state of the JTAG machines. This line is pulled up internally by the MSC8102.
11
VDD
P
Connect to 3.3V power supply bus via protection resistor. May be used for
Command Convertor power.
12
N.C.
-
Not Connected.
TRSTscb
I
Test port Reset. When this signal is active (Low), it resets the MSC8102
JTAG logic. This line is pull-down on the ADS with a 2.2KΩ resistor, to
provide continuous reset of the JTAG logic, when connector is unplugged.
13
14
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P15
13
1
14
2
Figure 5-3 P15 connector top view
5.5.9 P17 - EE1 Connector
EE1 two pins header on the ADS front side which provide MSC8102 debug request connectivity
on the another ADS boards. The pinout of P17 is shown in Table 5-15 "P17 - EE1 Chain Connector" below :
Table 5-15 P17 - EE1 Chain Connector
Pin No.
Signal Name
Attribute
Description
1
EE1in
I
Debug Request to the on-board MSC8102
2
EEout
O
Debug Request to MSC8102 mounted on another board (ADSs)
5.5.10 P20 - Ethernet Port Connector
The Ethernet connector on the MSC8102ADS - P20, is a Twisted-Pair (10-Base-T) compatible
connector. It is implemented with a 90o, 8-pin, RJ45 connector, signals of which are described in
Table 5-16 "P20 - Ethernet Port Interconnect Signals" below
Table 5-16 P20 - Ethernet Port Interconnect Signals
Pin
No.
Signal Name
Description
1
TPTX(GRAY)
Twisted-Pair Transmit Data positive output from the MSC8102ADS.
2
TPTX~(BROWN)
Twisted-Pair Transmit Data negative output from the MSC8102ADS.
3
TPRX(YELLOW)
Twisted-Pair Receive Data positive input to the MSC8102ADS.
4
(RED,GREEN)
Bob Smith terminated on the MSC8102ADS.
6
TPRX~(BLACK)
Twisted-Pair Receive Data negative input to the MSC8102ADS.
7
(BLUE,ORANGE)
Bob Smith terminated on the MSC8102ADS.
5
8
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Support Info
5.5.11 P23 Power Connector
P23 is 2mm Power Jack RAPC722 provide connection to external power supply [email protected].
5.5.12 J1 to J5 cPCI Connector
These connectors carry MSC8101 60x bus signals and MSC8102 peripheral signals out for offboard connection. :
Table 5-17 J1 - 60x Bus System Expansion
Pin No.
Signal Name
Attribute
Description
A1
-
N.C.
Not connected
A2
XTCK
O
JTAG Clock for off-board ADS placed at a backplane
A3
-
N.C.
Not connected
A4
XCS6
O
Chip Select 6 of the MSC8101
A5
XA18
O
60x Buffered Address Line 18
A6
IRQ2hb
I,P.U.
Interrupt 2 to the MSC8101. Pulled up on the ADS with a 10 KΩ
resistor.
A7
XD30
I/O
60x Buffered Data Line 30
A8
XD26
I/O
60x Buffered Data Line 26
A9
XBS3
O
Buffered Byte Select 3 Strobe
A10
XD21
I/O
60x Buffered Data Line 21
A11
XD18
I/O
60x Buffered Data Line 18
A12-A14
Not populated
-
-
A15, A17, A19,
A21, A23
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
A16
XHBCSb
O
Broadcast Chip Select for off-board ADS is associated with
MSC8101 CS3.
A17
XA12
O
60x Buffered Address Line 12
A20
XD12
I/O
60x Buffered Data Line 12
A22
XD7
I/O
60x Buffered Data Line 7
A24
XD1
I/O
60x Buffered Data Line 1
A25
N.C.
-
Not Connected
B1-B4
N.C.
-
Not Connected
B5
XA17
O
60x Buffered Address Line 17
B6, B8, B10, B16,
B18, B20, B22
GND
P
Digital Ground. Connected to main GND plane of the ADS.
B7
XD29
I/O
60x Buffered Data Line 29
B11
N.C.
-
Not Connected
B12-B14
Not populated
-
-
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Table 5-17 J1 - 60x Bus System Expansion
Pin No.
Signal Name
Attribute
Description
B15
XHCSb
O
Chip Select for off-board ADS is associated with MSC8101 CS4
B17
XA14
O
60x Buffered Address Line 14
B19
XD15
I/O
60x Buffered Data Line 15
B21
XD9
I/O
60x Buffered Data Line 9
B23
XD4
I/O
60x Buffered Data Line 4
B25
XA9
O
60x Buffered Address Line 9
C1
TRSThb
O
Reset to JTAG port for off-board ADS
C2
XTMS
O
TMS to JTAG port for off-board ADS
C3
N.C.
-
Not Connected
C4, C6, C8, C10,
C16, C18, C20,
C22, C24
GND
P
Digital Ground. Connected to main GND plane of the ADS.
C5
PRSTsb
O, O.D.
Power-On-Reset signal for Slaves (MSC8102)
C7
XD28
I/O
60x Buffered Data Line 28
C9
XD23
I/O
60x Buffered Data Line 23
C11
XD16
I/O
60x Buffered Data Line 16
C12-C14
Not populated
-
-
C15
XGPL2
O
Expansion General Purpose Line 2. This is buffered strobe which
assist MSC8101 UPM control over memory device if necessary.
May be used as OE for GPCM.
C17
XA13
O
60x Buffered Address Line 13
C19
XD14
I/O
60x Buffered Data Line 8
C21
XD8
I/O
60x Buffered Data Line 3
C23
XD3
I/O
60x Buffered Data Line 28
C25
XA7
O
60x Buffered Address Line 7
D1
N.C.
-
Not Connected
D2
TDOo
O
TDO signal is driven by off-board ADS.
D3
N.C.
-
Not Connected
D4
XA19
O
60x Buffered Address Line 19
D5, D7, D9, D11,
D17, D19
GND
P
Digital Ground. Connected to main GND plane of the ADS.
D6
CLKX
O
60x Buffered Bus Clock
D8
XD25
I/O
60x Buffered Data Line 25
D10
XD20
I/O
60x Buffered Data Line 20
D12-D14
Not populated
-
-
D15
N.C.
-
Not Connected
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Table 5-17 J1 - 60x Bus System Expansion
92
Pin No.
Signal Name
Attribute
Description
D16
GPL4(UPMWAIThb)
I/O, O.D.
Expansion General Purpose Line 4. This signal is configured as
UPMWAIThb Open Drain for Slaves
I/F and pulled up on the ADS with 10 KΩ resistor
D18
XA15
O
60x Buffered Address Line 15
D20
XD11
I/O
60x Buffered Data Line 11
D22
XD6
I/O
60x Buffered Data Line 6
D24
XD0
I/O
60x Buffered Data Line 0
D25
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
E1
N.C.
-
Not Connected
E2
TDIi
I
TDI signal is driven by the ADS to off-board.
E3,E4
N.C.
-
Not Connected
E5
HRST1b
I/O, O.D.
Hard Reset signal for off-board ADS located at first peripheral
slot. This signal is pulled up on the ADS with
10 KΩ resistor
E6
XD31
I/O
60x Buffered Data Line 31
E7
XD27
I/O
60x Buffered Data Line 27
E8
XD24
I/O
60x Buffered Data Line 24
E9
XD22
I/O
60x Buffered Data Line 22
E10
XD19
I/O
60x Buffered Data Line 19
E11
XBS2
O
Buffered Byte Select 2 Strobe
E12-E14
Not populated
-
-
E15
N.C.
-
Not Connected
E16
XA11
O
60x Buffered Address Line 11
E17
XA10
O
60x Buffered Address Line 10
E18
XBS1
O
Buffered Byte Select 1 Strobe
E19
XD13
I/O
60x Buffered Data Line 13
E20
XD10
I/O
60x Buffered Data Line 10
E21
XBS0
O
Buffered Byte Select 0 Strobe
E22
XD5
I/O
60x Buffered Data Line 5
E23
XD2
I/O
60x Buffered Data Line 2
E24
XA8
O
60x Buffered Address Line 8
E25
N.C.
-
Not Connected
F1-F25
Shield
-
Connected to chassis.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
Table 5-18 J2 - 60x Bus System Expansion
Pin No.
Signal Name
Attribute
Description
A1-A3
-
N.C.
Not connected
A4
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
A5
XBS5
O
Buffered Byte Select 5 Strobe
A6
XD63
I/O
60x Buffered Data Line 63
A7
XD59
I/O
60x Buffered Data Line 59
A8
XD56
I/O
60x Buffered Data Line 56
A9
XD52
I/O
60x Buffered Data Line 52
A10
XD49
I/O
60x Buffered Data Line 49
A11
XD45
I/O
60x Buffered Data Line 45
A12
XD42
I/O
60x Buffered Data Line 42
A13
XD38
I/O
60x Buffered Data Line 38
A14
XD35
I/O
60x Buffered Data Line 35
A15
XA21
O
60x Buffered Address Line 21
A16
XA24
O
60x Buffered Address Line 24
A17
XA25
O
60x Buffered Address Line 25
A18
XA29
O
60x Buffered Address Line 29
A19
GND
P
Digital Ground. Connected to main GND plane of the ADS.
A20-A22
-
N.C.
Not connected
B1, B3, B5, B7, B9,
B11, B13, B15,
B17, B19, B20, B21
GND
P
Digital Ground. Connected to main GND plane of the ADS.
B2
N.C.
-
Not Connected
B4
XA20
O
60x Buffered Address Line 20
B6
XD62
I/O
60x Buffered Data Line 62
B8
XD55
I/O
60x Buffered Data Line 55
B10
XD48
I/O
60x Buffered Data Line 48
B12
XD41
I/O
60x Buffered Data Line 41
B14
XD34
I/O
60x Buffered Data Line 34
B16
XA23
O
60x Buffered Address Line 23
B18
XA28
O
60x Buffered Address Line 28
B22
GA3
I, P.U.
Line 3 of Geographic Addressing sets up by jumper on the backplane. This signal is pulled up on the ADS with 10 KΩ resistor
C1
IRQ3hb
I,P.U.
Interrupt 3 to the MSC8101. Pulled up on the ADS with a 10 KΩ
resistor.
MSC8102ADSUM/D Ver. 1.2
User’s Manual
93
Support Info
Table 5-18 J2 - 60x Bus System Expansion
Pin No.
Signal Name
Attribute
Description
C2
SYSENb
O
This pin is grounded on the System Slot of the backplane that
allow to enable 60x bus strobes transceiver. Pulled up on the ADS
with a 10 KΩ resistor.
C3
HRESETsb
I/O, O.D.
Hard Reset signal for on-board Slave (MSC8102). This signal is
pulled up on the ADS with 1 KΩ resistor
C4
XBS7
O
Buffered Byte Select 7 Strobe
C5, C7, C9, C11,
C13
GND
P
Digital Ground. Connected to main GND plane of the ADS.
C6
XD61
I/O
60x Buffered Data Line 61
C8
XD54
I/O
60x Buffered Data Line 54
C10
XD47
I/O
60x Buffered Data Line 47
C12
XD40
I/O
60x Buffered Data Line 40
C14
XD33
I/O
60x Buffered Data Line 33
C15, C16
N.C.
-
Not Connected
C17
HRESEThb
I/O, O.D.
Hard Reset signal for on-board Host (MSC8101) provides PowerOn-Reset for off-board ADS. This signal is pulled up on the ADS
with 1 KΩ resistor
C18
XA27
O
60x Buffered Address Line 27
C19
XGPL0
O
Expansion General Purpose Line 0. This is buffered strobe which
assist MSC8101 UPM control over memory device if necessary.
May be used on a rear board.
C20
XGPL1
O
Expansion General Purpose Line 1. This is buffered strobe which
assist MSC8101 UPM control over memory device if necessary.
May be used on a rear board.
C21
XGPL3
O
Expansion General Purpose Line 3. This is buffered strobe which
assist MSC8101 UPM control over memory device if necessary.
May be used on a rear board.
C22
GA2
I, P.U.
Line 2 of Geographic Addressing sets up by jumper on the backplane. This signal is pulled up on the ADS with 10 KΩ resistor
D1
HRST2b
I/O, O.D.
Hard Reset signal for off-board ADS located at second peripheral
slot. This signal is pulled up on the ADS with
10 KΩ resistor
D2
HRST3b
I/O, O.D.
Hard Reset signal for off-board ADS located at third peripheral
slot. This signal is pulled up on the ADS with
10 KΩ resistor
D3
N.C.
-
Not Connected
D4, D6, D8, D10,
D12, D14, D16,
D18, D20
GND
P
Digital Ground. Connected to main GND plane of the ADS.
D5
XBS4
O
Buffered Byte Select 4 Strobe
D7
XD58
I/O
60x Buffered Data Line 58
D9
XD51
I/O
60x Buffered Data Line 51
D11
XD44
I/O
60x Buffered Data Line 44
94
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
Table 5-18 J2 - 60x Bus System Expansion
Pin No.
Signal Name
Attribute
Description
D13
XD37
I/O
60x Buffered Data Line 37
D15, D17
N.C.
-
Not Connected
D19
XPSDVALb
O
60x Buffered Data Valid Strobe. May be used on a rear board
D21
N.C.
-
Not Connected
D22
GA1
I, P.U.
Line 1 of Geographic Addressing sets up by jumper on the backplane. This signal is pulled up on the ADS with 10 KΩ resistor
E1
IRQ4hb
I,P.U.
Interrupt 4 to the MSC8101. Pulled up on the ADS with a 10 KΩ
resistor.
E2, E3
N.C.
-
Not Connected
E4
XBS6
O
Buffered Byte Select 6 Strobe
E5
XA16
O
60x Buffered Address Line 16
E6
XD60
I/O
60x Buffered Data Line 60
E7
XD57
I/O
60x Buffered Data Line 57
E8
XD53
I/O
60x Buffered Data Line 53
E9
XD50
I/O
60x Buffered Data Line 50
E10
XD46
I/O
60x Buffered Data Line 46
E11
XD43
I/O
60x Buffered Data Line 43
E12
XD39
I/O
60x Buffered Data Line 39
E13
XD36
I/O
60x Buffered Data Line 36
E14
XD32
I/O
60x Buffered Data Line 32
E15
N.C.
-
Not Connected
E16
XA22
O
60x Buffered Address Line 22
E17
N.C.
-
Not Connected
E18
XA26
O
60x Buffered Address Line 26
E19
BXBCTL0
O
Buffer Control Strobe 0. May be use on a rear board.
E20
BAh31
O
60x Buffered Address Line 31. May be use on a rear board.
E21
BAh30
O
60x Buffered Address Line 30. May be use on a rear board.
E22
GA0
I, P.U.
Line 0 of Geographic Addressing sets up by jumper on the backplane. This signal is pulled up on the ADS with 10 KΩ resistor
F1-F22
Shield
-
Connected to chassis
Table 5-19 J4 - H.110 Bus
Pin No.
Signal Name
Attribute
Description
A1
HTD0
I/O
Bus Data Line 0
A2
HTD4
I/O
Bus Data Line 4
MSC8102ADSUM/D Ver. 1.2
User’s Manual
95
Support Info
Table 5-19 J4 - H.110 Bus
96
Pin No.
Signal Name
Attribute
Description
A3
HTD8
I/O
Bus Data Line 8
A4
HTD11
I/O
Bus Data Line 11
A5
HTD13
I/O
Bus Data Line 13
A6
HTD16
I/O
Bus Data Line 16
A7
HTD19
I/O
Bus Data Line 19
A8
HTD21
I/O
Bus Data Line 21
A9
HTD24
I/O
Bus Data Line 24
A10
HTD27
I/O
Bus Data Line 27
A11
HTD29
I/O
Bus Data Line 29
A12-A25
Not in use
-
-
B1
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
B2
HTD5
I/O
Bus Data Line 5
B3
HTD9
I/O
Bus Data Line 9
B4
5V0
P
+5.0V Power. External power supply can feed the ADS via backplane.
B5
HTD14
I/O
Bus Data Line 14
B6
HTD17
I/O
Bus Data Line 17
B7
5V0
P
+5.0V Power. External power supply can feed the ADS via backplane.
B8
HTD22
I/O
Bus Data Line 22
B9
HTD25
I/O
Bus Data Line 25
B10
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
B11
HTD30
I/O
Bus Data Line 30
B12-B22
Not in use
-
-
B23
CT_RESETb
O
Reset to H.110 device on the ADS.
B24
N.C.
-
Not Connected
B25
HSGA3
I, P.U.
Line 3 of Shelf Enumeration sets up by jumper on the backplane.
This signal is pulled up on the ADS with 10 KΩ resistor
C1
HTD1
I/O
Bus Data Line 1
C2
HTD6
I/O
Bus Data Line 6
C3
HTD10
I/O
Bus Data Line 10
C4
HTD12
I/O
Bus Data Line 12
C5
HTD15
I/O
Bus Data Line 15
C6
HTD18
I/O
Bus Data Line 18
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
Table 5-19 J4 - H.110 Bus
Pin No.
Signal Name
Attribute
Description
C7
HTD20
I/O
Bus Data Line 20
C8
HTD23
I/O
Bus Data Line 23
C9
HTD26
I/O
Bus Data Line 26
C10
HTD28
I/O
Bus Data Line 28
C11
HTD31
I/O
Bus Data Line 31
C12-C22
Not in use
-
-
C23
CT_ENb
I, P.U.
This signal indicates that the ADS is fully seated into backplane.
Pull-up value is 2.4KΩ resistor
C24
N.C.
-
Not Connected
C25
HSGA2
I, P.U.
Line 2 of Shelf Enumeration sets up by jumper on the backplane.
This signal is pulled up on the ADS with 10 KΩ resistor
D1
HTD2
I/O
Bus Data Line 2
D2
HTD7
I/O
Bus Data Line 7
D3, D6, D7, D9
GND
P
Digital Ground. Connected to main GND plane of the ADS.
D4, D5
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
D8, D10
5V0
P
+5.0V Power. External power supply can feed the ADS via backplane.
D10
XD20
I/O
60x Buffered Data Line 20
D11-D24
Not in use
-
-
D25
HSGA1
I, P.U.
Line 1 of Shelf Enumeration sets up by jumper on the backplane.
This signal is pulled up on the ADS with 10 KΩ resistor
E1
HTD1
I/O
Bus Data Line 1
E2
GND
P
Digital Ground. Connected to main GND plane of the ADS.
E3
HSCLK_D
I/O
Skewed 8 MHz SCbus compatibility Data Clock
E4
HSCLK
I/O
8 MHz SCbus compatibility Data Clock
E5
HTNETREF_2
I/O
Secondary Telecom Network Timing Reference
E6
HTNETREF_1
I/O
Primary Telecom Network Timing Reference
E7
HT_C8_B
I/O
8 MHz redundant Data Clock
E8
HT_C8_A
I/O
8 MHz Data Clock
E9
HFR_COMP
I/O
8 KHz SCbus compatibility Frame Clock
E10
HT_FRAME_B
I/O
Redundant 8 KHz Frame Clock
E11
HT_FRAME_A
I/O
8 KHz Frame Clock
E12-E24
Not in use
-
-
E25
HSGA0
I, P.U.
Line 0 of Shelf Enumeration sets up by jumper on the backplane.
This signal is pulled up on the ADS with 10 KΩ resistor
MSC8102ADSUM/D Ver. 1.2
User’s Manual
97
Support Info
Table 5-19 J4 - H.110 Bus
Pin No.
Signal Name
Attribute
Description
F1-F15
GND
P
Digital Ground. Connected to main GND plane of the ADS.
F12-F20
Not populated
-
-
F21-F25
Shield
-
Connected to chassis.
Table 5-20 J5 - MSC8102 Signal Expansion Connector
Pin No.
Signal Name
Attribute
Description
A1
DSTo
O
Serial Data from CODEC
A2
N.C.
-
Not Connected
A3
L4TXD
O
MSC8101 TDM Port 4 Transmit Data
A4
GND
P
Digital Ground. Connected to main GND plane of the ADS.
A5
L4RXD
I
MSC8101 TDM Port 4 Receive Data
A6
L3TXD
O
MSC8101 TDM Port 3 Transmit Data
A7
L3RXD
I
MSC8101 TDM Port 3 Receive Data
A8
L2TXD
O
MSC8101 TDM Port 2 Transmit Data
A9
L2RXD
I
MSC8101 TDM Port 2 Receive Data
A10
L1TXD
O
MSC8101 TDM Port 1 Transmit Data
A11
L1RXD
I
MSC8101 TDM Port 1 Receive Data
A12
TD_A3
O
MSC8102 TDM Port 3 Transmit Data A channel
A13
RD_A3
I
MSC8102 TDM Port 3 Receive Data A channel
A14
TD_A2
O
MSC8102 TDM Port 2 Transmit Data A channel
A15
RD_A2
I
MSC8102 TDM Port 2 Receive Data A channel
A16
TD_A1
O
MSC8102 TDM Port 1 Transmit Data A channel
A17
RD_A1
I
MSC8102 TDM Port 1 Receive Data A channel
A18
TD_A0
O
MSC8102 TDM Port 0 Transmit Data A channel
A19
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
A20
RD_A0
I
MSC8102 TDM Port 0 Receive Data A channel
A21
TESTs
I,O
High active Test Signal for MSC8102.
A22
TIMER0
I/O
MSC8102 Timer 0.
B1
N.C.
-
Not Connected
B2, B4, B6, B8,
B10, B12, B14,
B16, B18, B20, B22
GND
P
Digital Ground. Connected to main GND plane of the ADS.
B3, B5
N.C.
-
Not Connected
98
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
Table 5-20 J5 - MSC8102 Signal Expansion Connector
Pin No.
Signal Name
Attribute
Description
B7
L4CLK
I
MSC8101 TDM Port 4 Data Clock
B9
L2CLK
I
MSC8101 TDM Port 2 Data Clock
B11
TDMCLK3
I
MSC8102 TDM Port 3 Data Clock
B13
TDMCLK2
I
MSC8102 TDM Port 2 Data Clock
B15
TDMCLK1
I
MSC8102 TDM Port 1 Data Clock
B17
TDMCLK0
I
MSC8102 TDM Port 0 Data Clock
B19
TIMER3
I/O
MSC8102 Timer 3
B21
TIMER1
I/O
MSC8102 Timer 1
C1
DSTi
I
Serial Data from CODEC
C2-C4
N.C.
-
Not Connected
C5
L3CLK
I
MSC8101 TDM Port 3 Data Clock
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
C7
L1CLK
I
MSC8101 TDM Port 1 Data Clock
C9
GPCLK1
O
Programmable General Purpose Clock1 from the TSI part (U16)
C11
GPCLK0
O
Programmable General Purpose Clock0 from the TSI part (U16)
C13
TD_B3
O
MSC8102 TDM Port 3 Transmit Data B channel
C15
TD_B2
O
MSC8102 TDM Port 2 Transmit Data B channel
C17
TD_B1
O
MSC8102 TDM Port 1 Transmit Data B channel
C19
TD_B0
O
MSC8102 TDM Port 0 Transmit Data B channel
C20
CCLK
I
CODEC Data Clock for Serial Microport
C21
GND
P
Digital Ground. Connected to main GND plane of the ADS.
C22
TIMER_CLK2
I/O
MSC8102 Timer 2
D1
F0
I
CODEC Frame Alignment
D2
N.C.
-
Not Connected
D3, D5, D7, D9,
D11, D17, D19
GND
P
Digital Ground. Connected to main GND plane of the ADS.
D4, D6
N.C.
-
Not Connected
D8
L3SYNC
I
MSC8101 TDM Port 3 Frame Sync
D10
L1SYNC
I
MSC8101 TDM Port 1 Frame Sync
D12
TDMSYN3
I
MSC8102 TDM Port 3 Frame Sync
D14
TDMSYN2
I
MSC8102 TDM Port 2 Frame Sync
D16
TDMSYN1
I
MSC8102 TDM Port 1 Frame Sync
D18
TDMSYN0
I
MSC8102 TDM Port 0 Frame Sync
D20
CDATA
I/O
CODEC Data I/O
C6, C8, C10, C12
C14, C16, C18
MSC8102ADSUM/D Ver. 1.2
User’s Manual
99
Support Info
Table 5-20 J5 - MSC8102 Signal Expansion Connector
Pin No.
Signal Name
Attribute
Description
D21
EE0s
I/O
MSC8102 Debug Reguest Pin (EE0)
D22
UARTRX
I
MSC8102 UART Recieve Pin
E1
N.C.
-
Not Connected
E2
TDIi
I
TDI signal is driven by the ADS to off-board.
E3,E4
N.C.
-
Not Connected
E5
HRST1b
I/O, O.D.
Hard Reset signal for off-board ADS located at first peripheral
slot. This signal is pulled up on the ADS with
10 KΩ resistor
E6
XD31
I/O
60x Buffered Data Line 31
E7
XD27
I/O
60x Buffered Data Line 27
E8, E10, E12, E15,
E17, E19
GND
P
Digital Ground. Connected to main GND plane of the ADS.
E9
XD22
I/O
60x Buffered Data Line 22
E10
XD19
I/O
60x Buffered Data Line 19
E11
XBS2
O
Buffered Byte Select 2 Strobe
E14
3V3
P
+3.3V Power. External power supply can feed the ADS via backplane.
E15
N.C.
-
Not Connected
E16
XA11
O
60x Buffered Address Line 11
E17
XA10
O
60x Buffered Address Line 10
E18
XBS1
O
Buffered Byte Select 1 Strobe
E19
XD13
I/O
60x Buffered Data Line 13
E20
XD10
I/O
60x Buffered Data Line 10
E21
XBS0
O
Buffered Byte Select 0 Strobe
E22
XD5
I/O
60x Buffered Data Line 5
E23
XD2
I/O
60x Buffered Data Line 2
E24
XA8
O
60x Buffered Address Line 8
E25
N.C.
-
Not Connected
F1-F22
Shield
-
Connected to chassis.
100
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
1
11
14
25
E
D
C
B
A
Figure 5-4 cPCI J1,J4 connectors view
1
22
E
D
C
B
A
Figure 5-5 cPCI J2,J5 connectors view
MSC8102ADSUM/D Ver. 1.2
User’s Manual
101
Support Info
5.6 Program Information
The MSC8102ADS has one programmable logic device - Altera CPLD, serving control and
stasus function on the ADS. It implemented an U18 EPM3256ATC144-7. The design is done in
Verilog HDL program format and is listed below:
102
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
// renoir header_start
//
// Module BCSR_L1.BCSR_main.Main
//
// Created:
//
by - msil_lab.UNKNOWN (PC287)
//
at - 11:34:53 05/09/01
//
// Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
//
// renoir header_end
`resetall
`timescale 1ns/10ps
module BCSR_main (
clk,extclk,Data,reset,A7,A8,A9,A10,A27,A28,A29,
/*nPSDVAL,*/nWE,nW_R,nCS0,nBCSR_CS,nATMCS,nFCSh,nHCS1,nHBCS,
DSItoSYS,nSYS64,nFCFG,MODCK1s,MODCK2s,SWOPT,nSTBUFEN,
nRS232EN_1,nRS232EN_2,nFETH_RST,nATM_RST,nFRM_RST,FRMtoTSI,nCODEC_EN,
nBOOTPh,nBOOTPs,nDBUFXEN,nDBUFBEN, GA, nPRSTs,
HEE0_In,HEE0_Out,HEE1_In,HEE1_Out,
SEE0_In,SEE0_Out,SEE1_In,EE1_misc_In, EE1_misc_Out,n32to64En,
SIGH_LED,SIGS_LED,SEE1_LED,nLED_EN,
Aborth_In, HReseth_In, SReseth_In, Aborts_In, HResets_In, SResets_In,
MODCK1h,MODCK2h,MODCK3h,MODCK4h,MODCK5h,MODCK6h,MODCKh_Out,
nHRESETh,nSRESETh,nHRESETs,nSRESETs,nHRST,nHRST_In,nNMIh,nNMIs,
BM_Out,CNFGS_Out,DSI64_Out,DSISYNC_Out,SWTE_Out,MODCK1s_Out,MODCK2s_Out,
RSTCFG_Out,TEST_EN,TEST_SIG
);
//*** General Definition ***//
`define ASSERTED
0
`define NEGATED
1
`define ACTIVE_LOW 0
`define ACTIVE_HIGH
1
`define PRESSED
0
`define RELEASED
1
`define WRITE
`define READ
1
0
`define From_BCSR
1
`define From_FLASH
0
parameter BCSR_ver
= 3'b010; // Current version of code is 2
parameter divpr
parameter divsee0
parameter div2st
= 12;
= 2;
= 5;//3; // 4 // to apply delay equals 'delay = extclk * 2**10' or 50usec@20Mhz
parameter div1st
= 13;//2;//16 // to apply delay equals 'delay = extclk * 2**20' or 50msec@20Mhz
parameter zero
= 1'b0;
parameter divd
= div2st;
MSC8102ADSUM/D Ver. 1.2
User’s Manual
103
Support Info
parameter divc
= div1st;
//*** Inputs ***//
input clk,
// From Host clock buffer
extclk,
reset;
// Clock from external clock oscillator
// Main Power-on-Reset
input A27,A28,A29,
// 60-x bus addresses lines
/*nPSDVAL*/nWE,nW_R,
//
and controls
nCS0,nBCSR_CS,nATMCS, // Chip selects
DSItoSYS,
// DIP-switch selectes Slave boot source
nSYS64,
// DIP-switch selectes Slave data bus distribution
nFCFG, // DIP-switch selectes Host boot source (BCSR or Flash)
MODCK1s,MODCK2s, // DIP-switch select MODCKl for the Slave
MODCK1h,MODCK2h,MODCK3h,
MODCK4h,MODCK5h,MODCK6h; // DIP-switch select MODCKl for the Host
input
nHCS1,nHBCS; // Chip Selects for Slaves
input
A7,A8,A9,A10; // Addresses together with nHCS1,2 & nHBCS for select Slaves on/off- board
input [0:3] GA;
// Geographic Address of System Board setting by on-CPCI backplane jumpers,
// default value equals 0xf
input
Aborth_In, Aborts_In,
// Pushbuttons of NMI for Host & Slave
HReseth_In, HResets_In, // Pushbuttons of HReset for Host & Slave
SReseth_In, SResets_In; // Pushbuttons of Sreset for Host & Slave
input
HEE0_In,HEE1_In; // Inputs from DIP-switch for Host EE0,1 control
input
SEE0_In,SEE1_In; // Inputs from DIP-switch for Slave EE0,1 control
input
EE1_misc_In; // Debug acknowledge comming from another ADS
input [0:2] SWOPT;
// Software options applied from DIP-switch
input [1:3] nHRST_In;
// Three HRESETs from external boards
//*** Bidirectional ***//
inout [0:7] Data; // Eight bit of buffered 60-x bus
inout
nHRESETh,nHRESETs, // HRESET for Host & Slave
nSRESETh,nSRESETs; // SRESET for Host & Slave
inout
nPRSTs;
inout
HEE1_Out;
// Wire connected to PORESET of Slave
// EE1 for Host
//*** Outputs ***//
output
nNMIh,nNMIs;
output
nFCSh,
// IRQ0 for Host & Slave
// Host Side Flash chip enable
nRS232EN_1,nRS232EN_2, // Enable for RS232 transmitters
nFETH_RST,nATM_RST,// Reset for ATM framer and Ethernet Phy
nFRM_RST,
// E1/T1 Farmer Reset
FRMtoTSI,
nCODEC_EN,
// Switch FALC56 channels to TSI or to TDM3 of 8102
// Chip select to CODEC device
nBOOTPh,nBOOTPs;
output
// Boot Sector protection for Flashes
HEE0_Out; // EE0 for Host
output
SEE0_Out; // EE0 for Slave
output
nDBUFXEN, // Enable for on-board periperals buffer
nDBUFBEN; // Enable for off-board periperals buffer to access to another boards
output
nSTBUFEN; // Enable for ext. buffer driven Board Configuration Identificator (BCONF[0:1])
// and Board Revision (BREVN[0:2]) when read from BCSR5
output [3:1] MODCKh_Out; // MODCK1-3 comming from DIP-switch for setting Host(8101) PLL mode
output [1:3] nHRST;
// Three HRESETs to external boards
//*** LEDs drive pins ***//
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output
nLED_EN;
// Allow to switch off all LEDs on the ADS accordingly to TTM req.
output [0:1] SIGH_LED, // Misc two LEDs for SW indication for Host
SIGS_LED; // Misc two LEDs for SW indication for Slave
output SEE1_LED; // Slave in-Debug Mode indication
//*** Slave configuration pins ***//
output [0:2] BM_Out;
output
output
// Boot Mode selection three bits for the
n32to64En; // Output for MUX control
CNFGS_Out, // Configuration Source
DSI64_Out, // DSI 64bit setting
DSISYNC_Out, // DSI Synchronous Mode
SWTE_Out, // Software Watchdog Timer Enable
RSTCFG_Out, // Reset Configuration Mode
MODCK1s_Out, // Two lines of MODCK
MODCK2s_Out;
`define CFGPINS
{BM_Out[0:2],CNFGS_Out,DSI64_Out,DSISYNC_Out,SWTE_Out,RSTCFG_Out,MODCK1s_Out,MODCK2s_Out}
// All the pins defined Slave PORESET configuration
//*** Test mode ***//
output TEST_EN; // Enter 8102 to test mode
output [1:3] TEST_SIG; // Select test mode
output
EE1_misc_Out;
//*** Registers Definition ***//
reg [0:7] DataO;
//**** BCSR0 Description ****//
reg [0:7] BCSR0;
`define
FLASHPRT1 BCSR0[0] // Flash 1 H/W Protection
`define
FLASHPRT2 BCSR0[1] // Flash 2 H/W Protection
`define FRM_RST BCSR0[2] // Framer E1/T1 Reset contol
`define CODEC_EN BCSR0[3] // CODEC Chip Select
`define
SIGNALS0 BCSR0[4] // Signal-0 LED Slave
`define
SIGNALS1 BCSR0[5] // Signal-1 LED Slave
`define
SIGNALH0 BCSR0[6] // Signal-0 LED Host
`define
SIGNALH1 BCSR0[7] // Signal-1 LED Host
//**** BCSR1 Description ****//
reg [0:7] BCSR1;
`define
RECONF BCSR1[0] // Start Slave Re-configuration
`define
HRST1 BCSR1[1] // Hard Reset to External Slave1
`define HRST2
BCSR1[2] // Hard Reset to External Slave2
`define ATM_RST BCSR1[3] // ATM Framer Reset
`define HRST3
BCSR1[4] // Hard Reset to External Slave3
`define FETH_RST BCSR1[5] // Fast Ethernet phy Reset
`define RS232EN_1 BCSR1[6] // RS232 Transceiver Host Side Enable
`define RS232EN_2 BCSR1[7] // UART Transceiver Slave Side Enable
//**** BCSR2 Description ****//
reg [0:7] BCSR2;
`define RSTCNF
`define
BCSR2[0] // Reset Configuration Mode
CNFG
`define SWTE
`define DSI64
`define DSISYNC
`define HRST
BCSR2[1] // Configuration Source
BCSR2[2] // Software Watchdog Timer Enable
BCSR2[3] // System/DSI 64/32 bit
BCSR2[4] // DSI Synchronous Mode
BCSR2[5] // Hard Reset to Slave
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`define SRST
BCSR2[6] // Soft Reset to Slave
`define FRMtoTSI BCSR2[7] // FALC56 connects to TSI or to TDM3 of 8102
//**** BCSR3 Description ****//
reg [0:7] BCSR3;
`define
CLKMD
`define
SEE0
`define
RSV34
`define
BCSR3[0:1] // Clock Mode Setting Bits 1-2 for Slave
BCSR3[2] // Slave Emulation Enable 0
BTMD
BCSR3[3:4] // Reserved two bits
BCSR3[5:7] // Boot Mode for Slave Bits 0-2
//**** BCSR6 Description ****//
reg [0:7] BCSR6;
`define
FLUNLCK1 BCSR6[0] // Flash 1 Protection Unlock
`define
FLUNLCK2 BCSR6[1] // Flash 2 Protection Unlock
`define LEDEN
BCSR6[2] // LED Enable| Hidden
`define
TEST
`define
TESTSIG
`define
MARK
BCSR6[3] // Test Mode Available|
BCSR6[4:6] // Test Mode Select
BCSR6[7] // Mark Bit
reg
PRSTs;
reg
HEE0_Out;
reg
SEE0_Out;
reg
EE1misc_Out;
| bits
|
reg [divsee0:0] SEE0_count;
reg NMIh,NMIs,HRESETh,SRESETh,HRESETs,SRESETs;
reg
clock_divider;
reg [divc:0] counter;
reg [divd:0] hhr,shr,nhr,hsr,ssr,nsr;
wire [1:0] CFG_ADDR = {A27,A28};
wire [2:0] BCSR_ADDR = {CFG_ADDR,A29};
wire READ_CFG_FROM_BCSR;
wire [0:7] CFG_BYTE3_DEF;
wire [0:7] BCSR4;
wire [5:7] BCSR5;
wire [0:3] SSEL;
// Bits 0-4 are comming via ext. buffer
// Address vector for Slaves Select
wire [0:3] ON_BRD_SLAVE_ADDR;
wire ON_BRD_HOST_PRPH; // Active when select any of Host peripheral
wire OFF_BRD_SLAVE;
// Active when access to off-board Slave
wire Write_to_BCSR;
wire Read_from_BCSR;
wire [0:7] BCSR1r,BCSR2r;
wire [0:7] BCSR2_PON_DSI,BCSR2_PON_SYS;//BCSR3_PON;
wire [0:1] BCSR3_PONh;
wire [0:4] BCSR3_PONl;
wire [0:2] BTMD;
wire ADDR3,ADDR5;
wire WRITE3;
wire [1:10] CFGREG;
wire RESET_ACTIVE;
//*** Hard Reset Configuration Word (HRCW) ***//
parameter
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EARB_DEF
= 1'b0,
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EXMC_DEF
= 1'b0,
nIRQ7INT_DEF = 1'b1,
EBM_DEF
= 1'b0,
BPS_DEF
= 2'b10,
SCDIS_DEF
= 1'b0,
ISPS_DEF
= 1'b0,
CFG_BYTE0_DEF =
// 0x28
{EARB_DEF,EXMC_DEF,nIRQ7INT_DEF,EBM_DEF,BPS_DEF,SCDIS_DEF,ISPS_DEF},
IRPC_DEF
= 2'b00,
DPPC_DEF
= 2'b00,
NMIOUT_DEF = 1'b0,
ISB_DEF
= 3'b000,
CFG_BYTE1_DEF =
// 0x0
{IRPC_DEF,DPPC_DEF,NMIOUT_DEF,ISB_DEF},
RSV16_DEF
= 1'b0,
BBD_DEF
= 1'b0,
MMR_DEF = 2'b11,
RSV20_21_DEF = 2'b00,
TCPC_DEF
= 2'b10,
CFG_BYTE2_DEF =
// 0x02
{RSV16_DEF,BBD_DEF, MMR_DEF,RSV20_21_DEF,TCPC_DEF},
BC1PC_DEF
= 2'b00,
RSV26_DEF
= 1'b0,
DLLDIS_DEF = 1'b0,
// MODCK_H_DEF = 3'b100,
RSV31_DEF
= 1'b0,
CFG_BYTE3_0_3DEF =
// 0x08
{BC1PC_DEF,RSV26_DEF,DLLDIS_DEF},
CFG_BYTE3_7DEF = RSV31_DEF;
//*** Power-on-Reset value of BCSR0-3, BCSR6 ***//
parameter
//*** BCSR0 PON value ***//
FLASHPRT1_PON = 1'b0,
FLASHPRT2_PON = 1'b0,
FRM_RST_PON = 1'b1,
CODEC_EN_PON = 1'b0,
SIGNALS0_PON = 1'b1,
SIGNALS1_PON = 1'b1,
SIGNALH0_PON = 1'b1,
SIGNALH1_PON = 1'b1,
BCSR0_PON = {FLASHPRT1_PON, FLASHPRT2_PON,FRM_RST_PON,
CODEC_EN_PON,SIGNALS0_PON,SIGNALS1_PON,
SIGNALH0_PON,SIGNALH1_PON
}, // 0x2f
//*** BCSR1 PON value ***//
RECONF_PON
= 1'b1,
HRST1_PON
= 1'b1,
HRST2_PON
= 1'b1,
ATM_RST_PON = 1'b1,
HRST3_PON
= 1'b1,
FETH_RST_PON = 1'b1,
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RS232EN_1_PON = 1'b1,
RS232EN_2_PON = 1'b1,
BCSR1_PON = {RECONF_PON,HRST1_PON,HRST2_PON,ATM_RST_PON,
HRST3_PON,FETH_RST_PON,RS232EN_1_PON,
RS232EN_2_PON
}, // 0xff
//*** BCSR2 PON value ***//
RSTCNF_PON
DSISYN_PON
HRST_PON
= 1'b0, // BCSR2.0
= 1'b0, // BCSR2.4
= 1'b1, // BCSR2.5
SRST_PON
= 1'b1, // BCSR2.6
FRMtoTSI_PON = 1'b1, // BCSR2.7
//*** BCSR3 PON value ***//
RSV34_PON
= 2'b11,
//*** BCSR6 PON value ***//
FLUNLCK1_PON = 1'b1,
FLUNLCK2_PON = 1'b1,
LEDEN
= 1'b0,
TEST
= 1'b0, // Disable Test Mode
TESTSIG
= 3'b0,
MARK
= 1'b0,
BCSR6_PON = {FLUNLCK1_PON, FLUNLCK2_PON, LEDEN, TEST,
TESTSIG, MARK}; // 0xd0
//*** Nodes ***//
assign READ_CFG_FROM_BCSR = (nCS0 == `ASSERTED) && (nHRESETh == `ASSERTED)
&& (nFCFG == `From_BCSR) && !nW_R;
assign SSEL[0:3]
= {A7,A8,A9,A10};
assign ON_BRD_SLAVE_ADDR = GA[0:3]; // Apply 0xf for any out-of-CPCI backplane configuration
assign ON_BRD_HOST_PRPH = !(nCS0 && nBCSR_CS && nATMCS);
assign OFF_BRD_SLAVE
assign nDBUFBEN
= ((SSEL != ON_BRD_SLAVE_ADDR) && !nHCS1) || (!nHBCS && nW_R);
= !(ON_BRD_HOST_PRPH || OFF_BRD_SLAVE);
// to prevent contention on the Data bus to external boards
assign nDBUFXEN
= !OFF_BRD_SLAVE;
assign Write_to_BCSR = /*!nPSDVAL && nW_R && */!nBCSR_CS;
assign Read_from_BCSR = !nW_R && !nBCSR_CS && nHRESETh;
assign BCSR2_PON_DSI = {RSTCNF_PON,2'b10,nSYS64,DSISYN_PON,HRST_PON,SRST_PON,FRMtoTSI_PON};
assign BCSR2_PON_SYS = {RSTCNF_PON,2'b01,nSYS64,DSISYN_PON,HRST_PON,SRST_PON,FRMtoTSI_PON};
assign BTMD
= DSItoSYS ? 3'b0 : 3'b001;
assign BCSR3_PONh = {MODCK1s,MODCK2s};
assign BCSR3_PONl
= {RSV34_PON,BTMD};
assign BCSR4
= {SEE0_In,SEE1_In,SWOPT[0:2],3'b111};
assign BCSR5
= BCSR_ver;
assign ADDR3
= !A27 && A28 && A29;
assign ADDR5
= A27 && !A28 && A29;
assign WRITE3
= Write_to_BCSR && ADDR3;
assign nSTBUFEN
= !(Read_from_BCSR && ADDR5);
assign BCSR1r[0:7]
= {`RECONF, nHRST_In[1:2],`ATM_RST,nHRST_In[3],`FETH_RST,`RS232EN_1,`RS232EN_2};
assign BCSR2r[0:7]
= {`RSTCNF, `CNFG, `SWTE , nSYS64, `DSISYNC, nHRESETs, nSRESETs,`FRMtoTSI};
assign CFG_BYTE3_DEF = {CFG_BYTE3_0_3DEF,MODCK4h,MODCK5h,MODCK6h,CFG_BYTE3_7DEF};
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assign CFGREG[1:10] = {`BTMD,`CNFG,`DSI64,`DSISYNC,`SWTE,`RSTCNF,MODCK1s,MODCK2s};
assign `CFGPINS
= (nPRSTs == `ASSERTED)? CFGREG[1:10] : 10'bz;
assign n32to64En
= !`DSI64;
//*** Outputs ***//
assign nLED_EN
= `LEDEN;
assign TEST_EN
= `TEST;
assign TEST_SIG[1:3] = (`TEST == `ACTIVE_HIGH)? `TESTSIG : 3'bz;
assign EE1_misc_Out = EE1_misc_In; // temporary Null-Logic
assign MODCKh_Out
assign nFCSh
= (nHRESETh == `ASSERTED)? {MODCK3h,MODCK2h,MODCK1h} : 3'bz;
= (nFCFG == `From_FLASH)? nCS0 : ((nHRESETh == `ASSERTED)? 1'b1 : nCS0);
assign FRMtoTSI
= `FRMtoTSI;
assign nBOOTPh
= ((`FLUNLCK1 == 1) && (`FLASHPRT1 == 0))? `ASSERTED : `NEGATED;
assign nBOOTPs
= ((`FLUNLCK2 == 1) && (`FLASHPRT2 == 0))? `ASSERTED : `NEGATED;
assign SIGH_LED[0] = (`LEDEN == `ACTIVE_LOW)? ((nSRESETh == `ASSERTED)? `ASSERTED : `SIGNALH0):
`NEGATED;
// Also indicates SRESET assertion
assign SIGH_LED[1] = (`LEDEN == `ACTIVE_LOW)? ((nHRESETh == `ASSERTED)? `ASSERTED : `SIGNALH1):
`NEGATED;
// Also indicates HRESET assertion
assign SIGS_LED[0] = (`LEDEN == `ACTIVE_LOW)? ((nSRESETs == `ASSERTED)? `ASSERTED : `SIGNALS0):
`NEGATED;
// Also indicates SRESET assertion
assign SIGS_LED[1] = (`LEDEN == `ACTIVE_LOW)? ((nHRESETs == `ASSERTED)? `ASSERTED : `SIGNALS1): `NE
GATED;
// Also indicates HRESET assertion
assign SEE1_LED
= (`LEDEN == `ACTIVE_LOW)? !SEE1_In : `NEGATED;
// Debug Acknowledge indication for the Slave
assign nCODEC_EN
= (`CODEC_EN == `ACTIVE_LOW)? `ASSERTED : `NEGATED;
assign nRS232EN_1
= (`RS232EN_1 == `ACTIVE_LOW)? `ASSERTED : `NEGATED;
assign nRS232EN_2
= (`RS232EN_2 == `ACTIVE_LOW)? `ASSERTED : `NEGATED;
assign nFETH_RST
= (`FETH_RST == `ACTIVE_LOW)||(nHRESETh == `ASSERTED)? `ASSERTED : `NEGATED;
assign nATM_RST
= (`ATM_RST == `ACTIVE_LOW) ||(nHRESETh == `ASSERTED)? `ASSERTED : `NEGATED;
assign nFRM_RST
= (`FRM_RST == `ACTIVE_LOW) ||(nHRESETh == `ASSERTED)? `ASSERTED : `NEGATED;
assign HEE1_Out
= (HEE1_In == `ASSERTED)? HEE1_In : 1'bz;
assign nNMIh
= ( NMIh == `ASSERTED)? `ASSERTED : `NEGATED;
assign nNMIs
= ( NMIs == `ASSERTED)? `ASSERTED : 1'bz;
//*** Resets Output *** //
assign nHRESETh
= ( HRESETh == `ASSERTED)? `ASSERTED : 1'bz ;
assign nSRESETh
= ( SRESETh == `ASSERTED)? `ASSERTED : 1'bz ;
assign nSRESETs
= (`SRST == `ACTIVE_LOW || SRESETs == `ASSERTED)? `ASSERTED : 1'bz;
assign nHRESETs
= (`HRST == `ACTIVE_LOW || HRESETs == `ASSERTED)? `ASSERTED : 1'bz;
assign nPRSTs
= ((`RECONF == `ACTIVE_LOW) || (nHRESETh == `ASSERTED)) ? `ASSERTED : 1'bz;
assign nHRST[1]
= (`HRST1 == `ASSERTED)? `HRST1 : `NEGATED;
assign nHRST[2]
= (`HRST2 == `ASSERTED)? `HRST2 : `NEGATED;
assign nHRST[3]
= (`HRST3 == `ASSERTED)? `HRST3 : `NEGATED;
assign RESET_ACTIVE = (reset == `ASSERTED) || (HRESETh == `ASSERTED);
//*** Execution Section ***//
//*** Generation Debug Request for Host ***//
always @ (posedge clk)
begin
HEE0_Out = HEE0_In; // No extra logic - may be added in future
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end
//*** Synchronous Slave Soft Reset ***//
reg nSRESETs_d1,nSRESETs_d2,nSRESETs_d3;
always @ (posedge extclk)
begin
if(nSRESETs == `ASSERTED)
else
nSRESETs_d1 <= `ASSERTED;
nSRESETs_d1 <= `NEGATED;
if(nSRESETs_d1 == `ASSERTED) nSRESETs_d2 <= `ASSERTED;
else
nSRESETs_d2 <= `NEGATED;
if(nSRESETs_d2 == `ASSERTED) nSRESETs_d3 <= `ASSERTED;
else
nSRESETs_d3 <= `NEGATED;
end
//*** Slave Debug Request logic ***//
always @ (posedge extclk)
begin
if(nSRESETs_d3 == `ASSERTED)
begin
SEE0_count = 0;
if (`SEE0 == `ASSERTED) SEE0_Out = 0;
else
SEE0_Out = 1;
end
else begin
if (WRITE3 && (Data[2] == 1)) begin
SEE0_count = 0; SEE0_Out = 0; // Produce short negage pulse
end
else begin
if (SEE0_count[divsee0] != 1) begin
SEE0_count = SEE0_count + 1; SEE0_Out = 0; // Activate Debug Request at rising edge
end
else SEE0_Out = !SEE0_In; // Permanent State of Debug Request pin
end
end
end
//**** BCSR Register Main ****//
assign Data[0:7]
= DataO[0:7];
always @ (CFG_ADDR or READ_CFG_FROM_BCSR or BCSR_ADDR or Read_from_BCSR)
if(READ_CFG_FROM_BCSR)
case (CFG_ADDR)
2'b00 : DataO[0:7] = CFG_BYTE0_DEF;
2'b01 : DataO[0:7] = CFG_BYTE1_DEF;
2'b10 : DataO[0:7] = CFG_BYTE2_DEF;
2'b11 : DataO[0:7] = CFG_BYTE3_DEF;
endcase
else if(Read_from_BCSR)
case (BCSR_ADDR)
0 : DataO[0:7] = BCSR0[0:7];
1 : DataO[0:7] = BCSR1r[0:7];
2 : DataO[0:7] = BCSR2r[0:7];
3 : DataO[0:7] = {BCSR3[0:1],SEE0_Out,BCSR3[3:7]};
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4 : DataO[0:7] = BCSR4[0:7];
5 : DataO[0:7] = {5'bz,BCSR5[5:7]};
6 : DataO[0:7] = BCSR6[0:7];
endcase
else DataO[0:7] = 8'bz;
//**** BCSR Register Power-on-Reset setting & Write ****//
always @ (posedge nWE or negedge nHRESETh) // or negedge reset)
begin
if(nHRESETh == `ASSERTED)
begin
BCSR0[0:7] = BCSR0_PON; // general
BCSR1[0:7] = BCSR1_PON; // board
BCSR6[0:7] = BCSR6_PON; // initialize
{BCSR3[0:1],BCSR3[3:7]} = {BCSR3_PONh,BCSR3_PONl};
if (!DSItoSYS) BCSR2[0:7] = BCSR2_PON_DSI;
else
BCSR2[0:7] = BCSR2_PON_SYS;
end
else begin
if (nHRESETs == `ASSERTED) `SEE0 = !SEE0_In; // Debug request to Slave
if (Write_to_BCSR)
case (BCSR_ADDR)
0: begin
if(Data[0] == 1'b1)
if(`FLUNLCK1 == `ASSERTED) `FLASHPRT1 = `NEGATED;
else `FLASHPRT1 = `ASSERTED;
if(Data[1] == 1'b1)
if(`FLUNLCK2 == `ASSERTED) `FLASHPRT2 = `NEGATED;
else `FLASHPRT2 = `ASSERTED;
BCSR0[2:7] = Data[2:7];
end
1: BCSR1[0:7] = Data[0:7];
2: {BCSR2[0:2],BCSR2[4:7]} = {Data[0:2],Data[4:7]};
3: BCSR3[0:7] = Data[0:7];
6: if (Data[7] == 1) BCSR6[0:6] = Data[0:6];
endcase
end
end
//**** Debounce functions ***//
function hhtime_elaps;
input i;
input [divd:0] d;
begin
// if (reset == `ASSERTED) begin hhtime_elaps = 1'bz; hhr = 1 << d; end
// else begin
if (i == 0) hhr = 0;
else begin
if (hhr[d] != 1) begin
hhr = hhr + 1; hhtime_elaps = 1'b0;
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end else hhtime_elaps = 1'b1;
end
//end
end
endfunction
function shtime_elaps;
input i;
input [divd:0] d;
begin
// if (reset == `ASSERTED) begin shtime_elaps = 1'bz; shr = 1 << d; end
// else
if (i == 0) shr = 0;
else begin
if (shr[d] != 1) begin
shr = shr + 1; shtime_elaps = 1'b0;
end else shtime_elaps = 1'b1;
end
end
endfunction
function nhtime_elaps;
input i;
input [divd:0] d;
begin
// if (reset == `ASSERTED) begin nhtime_elaps = 1'bz; nhr = 1 << d; end
// else
if (i == 0) nhr = 0;
else begin
if (nhr[d] != 1) begin
nhr = nhr + 1; nhtime_elaps = 1'b0;
end else nhtime_elaps = 1'b1;
end
end
endfunction
function hstime_elaps;
input i;
input [divd:0] d;
begin
// if (reset == `ASSERTED) begin hstime_elaps = 1'bz; hsr = 1 << d; end
// else
if (i == 0) hsr = 0;
else begin
if (hsr[d] != 1) begin
hsr = hsr + 1; hstime_elaps = 1'b0;
end else hstime_elaps = 1'b1;
end
end
endfunction
function sstime_elaps;
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User’s Manual
Support Info
input i;
input [divd:0] d;
begin
// if (reset == `ASSERTED) begin sstime_elaps = 1'bz; ssr = 1 << d; end
// else
if (i == 0) ssr = 0;
else begin
if (ssr[d] != 1) begin
ssr = ssr + 1; sstime_elaps = 1'b0;
end else sstime_elaps = 1'b1;
end
end
endfunction
function nstime_elaps;
input i;
input [divd:0] d;
begin
// if (reset == `NEGATED)
if (i == 0) nsr = 0;
else begin
if (nsr[d] != 1) begin
nsr = nsr + 1; nstime_elaps = 1'b0;
end else nstime_elaps = 1'b1;
end
end
endfunction
//repeat(div1st) @(posedge clk);
always @ (posedge extclk)
begin
if (reset == `ASSERTED)
begin
counter = (1 << div1st) - 2;
// hhr = 1 << div2st; shr = 1 << div2st; hsr = 1 << div2st; /
// ssr = 1 << div2st; nhr = div2st << div2st; nsr = 1 << div2st;
end
counter = counter + 1;
if (counter[div1st] != 1) clock_divider = 0;
else
clock_divider = 1;
end
always @ (posedge clock_divider)
begin
if
else
if
else
if
(HReseth_In == `PRESSED) HRESETh = hhtime_elaps(0,div2st);
HRESETh = hhtime_elaps(1,div2st);
(SReseth_In == `PRESSED) SRESETh = shtime_elaps(0,div2st);
SRESETh = shtime_elaps(1,div2st);
(Aborth_In == `PRESSED) NMIh = nhtime_elaps(0,div2st);
else
NMIh = nhtime_elaps(1,div2st);
else
NMIs = nstime_elaps(1,div2st);
end
endmodule //BCSR_main
MSC8102ADSUM/D Ver. 1.2
User’s Manual
113
Support Info
5.7 Schematics Drawing
114
MSC8102ADSUM/D Ver. 1.2
User’s Manual
Support Info
5
Table of Contents
This Page
Description
Bus Configuration Diagram
Page
1
Memory for Host/Slave Sides
2
BCSR & JTAG Logic
Buffers for Host/Slave Sides
5
MSC8101 CPM and COM Peripherals
Host Processor (MSC8101) - Part I
6
3
7
MSC8102 TDM Peripherals
Slave DSP (MSC8102)
4
8
CODEC and UART
9
10
Pull-Up / Pull-Down Resistors
cPCI Expansion Connectors
Parts Powering
Logic Analyzer Connectors - Mictors
13
Power Supplies, LEDs
11
14
12
15
MSIL: 084-8 102ADS-5
PCB: 084-00160-2
4
4
3
Revision History
1. Added Network clock to T SI PLL sync source.
2. Bus switch U8 avoids contention on TD_A(B)3 lines when
TSI and E1/T1 Framer work together.
PILOT:
3
2
2
xx
xx
xx
xx
LEGEND:
1
On-pag e signal connection
1
Sheet
Off-pa ge signal connection
Signal has pull-up
Signal has pull-down
Motorola Semiconductor Israel Ltd.
MSC8102ADS
Contents
Tuesday, August 13, 2002
Document Number
Metrowerks Israel
1 Shen kar street
Herzelia 46120 Isra el
Title
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115
MSC8102ADSUM/D Ver. 1.2
User’s Manual
D
C
B
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5
Figure 5-6 Schematics. Page 1
Support Info
5
8
8
E1/T1
Framer
BAs[24:31]
BAs[24:31]
p.4
4
32
SDRAM2-1
32
SDRAM2-2
8MB
p.4
[0:31]
SYSTEM [0:31]
SLAVE
8102
DATA
SYS TEM/DSI [32:63]
p.8
4
32
[0:31]
[11:29]
ADDRESS
[0:31]
DSI[0:31]
DSI Bus
3
Data Bus
Switch
Ctrl
Dh[32:63]
Dh[6:31]
Dh[0:5]
Config
Signals
Dh[0:63]
DATA[0:63]
HOST
8101
p.3
ADDRESS[7:31]
Dh[16:63]
Dh[0:15]
Dh[0:63]
64
Ah[18:28]
p.4
SDRAM1
p.5
8MBx2
p.4
2
BD[0:15]
p.4
16
16
XAt[24:31]
24Ohm
XAt[9:29]
BAh30
2
8
FLASH
p.5
4MB
XD[16:63]
p.4
BD[0:7]
ATM
Framer
p.7
XD[0:15]
p.6
BCSR
XA[7:29]
BD[0:7]
XAt[27:29]
XD[0:63]
cPCI CON
p.12
Motorola Se miconductor Israel Ltd.
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
Document Nu mber
1
1
Sh eet
Bus ConfigDiagram
MSC8102ADS
Tuesday, Augus
t 13, 2002
Date:
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C
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of
15
PIL OT
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Figure 5-7 Schematics. Page 2
p.4
Data Bus
Switch
p.8
PRSTs
Ah[7:29]
3
P1/P2
Ds[32:63]
Ds[0:31]
Ctrl
As[9:31]
SYST EM Bus
BDs[0:7]
8
8MB
FLASH
4MB
p.5
Ctrl
ADDR Bus
Switch
CKE p.5
As[9:23]
p.5
p.4
As[17:28]
or
As[18:29]
Note :
1. Ctrl means contr ol by BCSR
2. DSI bus is available for asynchr onous access only
As[17:28]
TSI Device
p.9
BAs[24:31]
D
C
p.9
5
MSC8102ADSUM/D Ver. 1.2
User’s Manual
116
B
A
BAs[27:31]
Support Info
D
5
8,1 1,13
11,1 2,13
11,1 2,13
11,1 2,13
8,1 1,13
7, 13
5,1 1,13
IRQ1hb
IRQ2hb
IRQ3hb
IRQ4hb
IRQ5hb
IRQ6hb
IRQ7hb
11 TTh1
DQ Mh0
DQ Mh1
DQ Mh2
DQ Mh3
DQ Mh4
DQ Mh5
DQ Mh6
DQ Mh7
MODCK h1
6, 11
0
R 196
6
TD Oh
6
TD Ih
4,6 ,13
TC Kh
6,1 2,13 TRSThb
4,6
TMSh
R 195
IRQ1 hb
IRQ2 hb
IRQ3 hb
IRQ4 hb
IRQ5 hb
IRQ6 hb
IRQ7 hb
TP62
TBST bh
4
3
1
2
ABB hb
TShb
AACK hb
A RTRYhb
DBBhb
TAhb
TEAhb
NM Ihb
R N50B
3 22.
R N47A
2 22.
RN4 7C
3 22.
RN 42D
3 22.
PSDVA Lhb
7
6 RN 50C
22. 8
7 RN 47B
22. 6
6 RN4 2C
22. 5
6 RN4 4C
22.
0
R149
10k
4,5, 8,11 Ah[3 1:0]
EXTCL Kh 6
TC Kh
TRSThb
RSTCNF hb
BNKSE Lh2
BNKSE Lh1
EE 4h
EE 5h
R182
UPM WAIThb
8 R N42A 1
5 RN 47D 4 22.
22. 5 RN 44D 4
7 R N42B 2 22.
22.
3V3
C LOCKh
SRE SEThb
HRES EThb
PR STb
EE 1h
EE 0h
D LLINh
R150
10k
EE 5h
R153
1k
(*)
C2
B1
D4
B2
C3
A2
D5
F6
N13
N12
U14
V14
W14
V13
W13
W12
N11
U13
D18
D19
B19
C19
H14
H13
H17
V12
V11
T13
T12
U12
B18
C18
J13
G17
U5
V5
G13
W11
L19
F19
H18
K18
K17
K14
J19
H19
D17
B17
F17
J17
J18
E19
G19
F14
E17
D3
C1
P8
W6
F2
F3
E1
E2
E3
D1
D2
U6
W4
V6
W5
G18
F18
E18
N8
F1
H6
G4
G3
G2
U 26A
4
DP0/EXT_BR2
DP1/IRQ1/EXT_BG2
DP2/IRQ2/EXT_DBG2
DP3/IRQ3/EXT_BR3
DP4/IRQ4/EXT_BG3/DREQ3
DP5/IRQ5/EXT_DBG3/DREQ4
DP6/IRQ6/DACK3
DP7/IRQ7/DACK4
TT0
TT1
TT2
TT3
TT4
TSIZ0
TSIZ1
TSIZ2
TSIZ3
TBST
GBL/IRQ1
BADDR27
BADDR28
BADDR29/IRQ2
BADDR30/IRQ3
BADDR31/IRQ5
BR
BG
ABB/IRQ2
TS
AACK
ARTRY
DBG
DBB/IRQ3
TA
TEA
NMI
NMI_OUT
PSDVAL
IRQ7/INT_OUT
BCTL1
BCTL0
ALE
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDAMUX/PGPL5
PGTA/PUPMWAIT/PGPL4/PPBS
PSDCAS/PGPL3
POE/PSDRAS/PGPL2
PSDWE/PGPL1
PSDA10/PGPL0
THERM2
THERM1
DLL_IN
TEST
EED
EE5
EE4
EE3
EE2
EE1
EE0
MODCK3/TC2/BNKSEL2
MODCK2/TC1/BNKSEL1
MODCK1/TC0/BNKSEL0
RSTCONF
SRESET
HRESET
PORESET
TDO
TDI
TCK
TRST
TMS
CLKIN
60X BUS
CONT ROL & CLOCK & RESET
11 ,13 TShb
13 ,15 DBBhb
11 ,13 TAhb
11 ,13 TEAhb
6, 13 NM Ihb
4,1 1,13 PSDVA Lhb
UPMW AIThb
CAShb
RAShb
W Ehb
SDA10h
4, 11 BC TL0hb
8,11 ,13
4, 11
4,5, 8,11
4,5 ,11
4,5 ,11
6,1 1,13 EE 1h
6,1 1,13 EE 0h
66.0MHz
5
DIP
6,11 ,13 SRE SEThb
6,11, 12,13 HRES EThb
5,6,1 1,15 PR STb
6,11 BNKSELh [1:2]
3V3
8
GND
OUT
VCC
U 31
4,5, 8,11 DQMh[ 0:7]
C272
0.1uF
4
Socket 8P
0
Note: SIUMCR/ESE = 1 fo r GBL enable
EE4h
R154
1k
(*)
BNKSE Lh2
BNKSE Lh1
UPMW AIThb
1 R N44A 8
22.
2 R N44B 7
22.
R161
22 .1
GP L4
BNKh1
BNKh0
12
5
5
*R129 is not assembled for PLL function.
For buffer function it shou ld be mounted.
4
3
MSC8101
SYSTEM
Bottom Vi ew
MSC8101
FR4
C 44
C 45
1
4
13
8
9
1
5
12
3
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
CY 2309ZC-1H
GND1
GND2
S2
S1
REF
VCC1
VCC2
PLL CLK-DRIVER
U 55
10uF
2
0.01 uF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
3V3
R135
10k
CLKO UTh
R129
0
(*)
+
C
B
A
5
2
3
14
15
6
7
10
11
VDDH
VDDH
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
RN 53C 6
5 2 2.
RN 50D 5
8 2 2.
R N53A 8
7 2 2.
CLKOUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCSYN
GNDSYN
VCCSYN1
GNDSYN1
3
4 RN5 3D
22. 4
1 RN 50A
22. 1
2 RN 53B
22.
SYSCLK1-1 5
D LLINh
BC SRCLK 6
SYSCLK1-2 5
CL KM1 11
CL KM2 11
CL KM3 11
SYS CLK 4
2
Dh[63: 0] 4,5, 8,11
R183
0
0.01 uF
C231
1V 5h
C254
C245
C246
C233
C227
0.01 uF
0.01 uF
0.01 uF
0.01 uF
0.01 uF
0.01 uF
0.01 uF
0.01 uF
C252
0.01 uF
C238
3V3 IOh
C239
C255
C258
C226
0.01 uF
0.01 uF
0.01 uF
0.01 uF
0.01 uF
0.01 uF
C225
C251
C244
C243
0.01 uF
CS0 hb 6, 11
B CSRCSb 6, 11
SDRMCS hb 5, 11
H BCSb 4,6, 8,11
HC Sb 4,6, 8,11
ATMCSb 6,7 ,11
CS6 hb 4, 11
CLKO UTh
C256
VCCSY N2
C 257 0.01 uF
VCCSY N1
3V3 Qh
E4
T15
E5
E9
E12
F4
F16
H16
L4
L16
N4
P16
R8
R11
R13
J4
M4
K5
R6
R7
R10
G5
N15
K16
G15
J16
E10
E8
E6
E11
E13
E15
R15
N16
R9
J15
G16
R12
R14
W7
V7
T7
U7
T8
F5
F7
F9
F11
F13
F15
G6
G8
G10
G12
G14
H5
H7
H15
J5
J6
J14
K6
K7
K13
K15
L5
L6
L14
L15
M5
M15
N6
N9
P6
P7
P9
P11
P12
P13
P14
P15
2
For signal SYSCLK1-1, SYSCLK1-2 & DLL INh
keep trace lengths equ al
16
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
M18
L13
M17
M19
L18
K19
L17
M16
SPARE5
SPARE1
U11
R2
GNDPLLh
1
FJS332 -702GG
Socket Adv.T ech.
1
Sh eet
3
Host MSC8101 - Part I
of
FJA332 -700G
Adapter A dv.Tech.
Socket/Ad apter System
Note: The part may be mounted on soc kets
Socket 3M 332pin
233 2-9025-01-1501
Motorola Se miconductor Israel Ltd.
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
Document Nu mber
MSC8102ADS
Tuesday, Augus
t 13, 2002
Date:
Size
C
15
PIL OT
R ev
D
C
B
A
117
MSC8102ADSUM/D Ver. 1.2
User’s Manual
D h0
D h1
D h2
D h3
D h4
D h5
D h6
D h7
D h8
D h9
Dh10
Dh11
Dh12
Dh13
Dh14
Dh15
Dh16
Dh17
Dh18
Dh19
Dh20
Dh21
Dh22
Dh23
Dh24
Dh25
Dh26
Dh27
Dh28
Dh29
Dh30
Dh31
Dh32
Dh33
Dh34
Dh35
Dh36
Dh37
Dh38
Dh39
Dh40
Dh41
Dh42
Dh43
Dh44
Dh45
Dh46
Dh47
Dh48
Dh49
Dh50
Dh51
Dh52
Dh53
Dh54
Dh55
Dh56
Dh57
Dh58
Dh59
Dh60
Dh61
Dh62
Dh63
B3
A3
C4
B4
A4
C5
B5
A5
D6
C6
B6
A6
G7
E7
D7
C7
B7
A7
F8
D8
C8
B8
A8
G9
D9
C9
B9
A9
F10
D10
C10
B10
A10
G11
D11
C11
B11
A11
F12
D12
C12
B12
A12
D13
C13
B13
A13
E14
D14
C14
B14
A14
D15
C15
B15
A15
E16
D16
C16
B16
A16
C17
A17
A18
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32/HD0
D33/HD1
D34/HD2
D35/HD3
D36/HD4
D37/HD5
D38/HD6
D39/HD7
D40/HD8
D41/HD9
D42/HD10
D43/HD11
D44/HD12
D45/HD13
D46/HD14
D47/HD15
D48/HA0
D49/HA1
D50/HA2
D51/HA3
D52/HCS
D53/HRD~/HRW
D54/HWR/HDS
D55/HTRQ/HREQ
D56/HRRQ/HACK
D57/HDSP
D58/HDDS
D59/H8BIT
D60/HCS2
D61
D62
D63
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
W15
N14
V15
T14
U15
W16
V16
W17
U16
V17
W18
U17
T16
V18
V19
R16
T17
U18
U19
R17
T18
M13
T19
P17
R18
R19
M14
P18
N17
P19
N18
N19
Ah0
Ah1
Ah2
Ah3
Ah4
Ah5
Ah6
Ah7
Ah8
Ah9
Ah 10
Ah 11
Ah 12
Ah 13
Ah 14
Ah 15
Ah 16
Ah 17
Ah 18
Ah 19
Ah 20
Ah 21
Ah 22
Ah 23
Ah 24
Ah 25
Ah 26
Ah 27
Ah 28
Ah 29
Ah 30
Ah 31
Figure 5-8 Schematics. Page 3
Support Info
3,5, 8,11 Ah[31 :7]
C220
3V3
3,5,8 ,11 DQM h0
3,5,8 ,11 RAShb
C 202 C 221
3,5,8 ,11 Dh[63: 0]
C201
0.1uF 0.1 uF 0.1 uF 0.1uF
5
Ah7
Ah8
Ah9
Ah 10
Ah 11
XSTRBENb
47
46
44
43
41
40
38
37
1
48
A8
A9
A10
A11
A12
A13
A14
A15
T/R2
OE2
4
7
41
44
12
15
33
36
20
23
25
28
1k
A5
A6
B5
B6
C5
C6
D5
D6
A3
A4
E5
E6
F5
F6
G5
G6
H6
H5
H4
H3
U 27A
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1OE
2OE
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
2
3
5
6
8
9
11
12
B Dh8
B Dh9
BDh10
BDh11
BDh12
BDh13
BDh14
BDh15
B Dh0
B Dh1
B Dh2
B Dh3
B Dh4
B Dh5
B Dh6
B Dh7
C242
C249
3V3
C 250 C 241
22.
1 RN 54A 8
2 RN 54B 7
3 RN5 4C 6
XA7
XA8
XA9
XA10
XA11
A5
A6
B5
B6
C5
C6
D5
D6
A3
A4
XA12
XA13
XA14
XA15
XA16
XA17
XA18
XA19
Dh32
Dh33
Dh34
Dh35
Dh36
Dh37
Dh38
Dh39
E5
E6
F5
F6
G5
G6
H5
H6
H3
H4
B Dh8
B Dh9
BDh10
BDh11
BDh12
BDh13
BDh14
BDh15
B Dh0
B Dh1
B Dh2
B Dh3
B Dh4
B Dh5
B Dh6
B Dh7
E5
E6
F5
F6
G5
G6
H5
H6
H3
H4
A5
A6
B5
B6
C5
C6
D5
D6
A3
A4
5,6 ,7
BDh[15 :0]
Dh40
Dh41
Dh42
Dh43
Dh44
Dh45
Dh46
Dh47
4
BWE0hb 5,7
BPOE hb 5,7
BW Eb
DBUFXE Nb
2A1
2A2
2A3
2A4
2A5
2A6
2A8
2A7
DIR2
OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
DIR1
OE1
U 20A
2A1
2A2
2A3
2A4
2A5
2A6
2A8
2A7
DIR2
OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
DIR1
OE1
U 21A
3,5 ,11 W Ehb
3, 11 CAShb
3,5 ,11 SDA1 0h
3, 11 BC TL0hb
XADRB ENb
XSTRBENb
0.1uF 0.1uF 0.1 uF 0.1 uF
A2
A1
B2
B1
C2
C1
D2
D1
5
E2
E1
F2
F1
G2
G1
H1
H2
DBUFXE Nb
6, 13
A[0: 9]
13
14
16
17
19
20
22
23
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
SN74LVC322 44GKER
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
3OE
4OE
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
A11
5
BXBCT L0 6,12
0.1 uF
C 31
3V3
A8
A9
A4
A5
A6
A7
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
T/R1
OE1 74LC X16245D
U 19
R181
Ah 12
Ah 13
Ah 14
Ah 15
Ah 16
Ah 17
Ah 18
Ah 19
D h0
D h1
D h2
D h3
D h4
D h5
D h6
D h7
XADR BENb
D h8
D h9
Dh10
Dh11
Dh12
Dh13
Dh14
Dh15
U45A
IA0
IA1
IB0
IB1
IC0
IC1
ID0
ID1
E
S
U45B
IA0
IA1
IB0
IB1
IC0
IC1
ID0
ID1
E
S
U4 5C
IA0
IA1
IB0
IB1
IC0
IC1
ID0
ID1
E
S
PI3B33X257B
YA
YB
YC
YD
PI3B33X257B
YA
YB
YC
YD
PI3B33X257B
YA
YB
YC
YD
36
35
33
32
30
29
27
26
24
25
22 .1
DB UFBENb
R119
43 .2
31
17
18
19
21
22
27
26
30
29
39
9
10
11
13
14
35
34
38
37
47
1
2
3
5
6
43
42
46
45
R108
As29
As28
As27
As26
As25
As24
As23
As22
As21
As20
As19
As18
As17
32to6 4ENb
4
R148
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B8
2B7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B8
2B7
Ah 20
Ah 21
Ah 22
Ah 23
Ah 24
Ah 25
Ah 26
Ah 27
Ah 28
Ah 29
Ah 30
Ah 31
1k
A2
A1
B2
B1
C2
C1
D2
D1
J5
J6
K5
K6
L5
L6
M5
M6
J3
J4
N5
N6
P5
P6
R5
R6
T6
T5
T4
T3
U 27B
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1OE
2OE
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
C 230 C 229
N2
N1
P2
P1
R2
R1
T1
T2
J2
J1
K2
K1
L2
L1
M2
M1
C236
43.
C235
3V3
3
J5
J6
K5
K6
L5
L6
M5
M6
J3
J4
5,7 ,12
7, 12
12
12
12
2A1
2A2
2A3
2A4
2A5
2A6
2A8
2A7
DIR2
OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
DIR1
OE1
U 20B
2A1
2A2
2A3
2A4
2A5
2A6
2A8
2A7
DIR2
OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
DIR1
OE1
U 21B
BA h30
BA h31
XGPL1
XGPL3
XGPL0
BB CTL0
Dh48
Dh49
Dh50
Dh51
Dh52
Dh53
Dh54
Dh55
N5
N6
P5
P6
R5
R6
T5
T6
T3
T4
2 R N40B 7
3 RN4 0C 6
1 R N40A 8
XA28
XA29
XA20
XA21
XA22
XA23
XA24
XA25
XA26
XA27
0.1 uF 0.1 uF 0.1uF 0.1uF
C 215 C 214
3V3
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
SN74LVC322 44GKER
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
3OE
4OE
C206
0.1uF 0.1uF 0.1 uF 0.1 uF
C205
XD32
XD33
XD34
XD35
XD36
XD37
XD38
XD39
Dh56
Dh57
Dh58
Dh59
Dh60
Dh61
Dh62
Dh63
J5
J6
K5
K6
L5
L6
M5
M6
J3
J4
XD40
XD41
XD42
XD43
XD44
XD45
XD46
XD47
Dh16
Dh17
Dh18
Dh19
Dh20
Dh21
Dh22
Dh23
E2
E1
F2
F1
G2
G1
H2
H1
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
N5
N6
P5
P6
R5
R6
T5
T6
T3
T4
XD[ 31:0]
8,12
A2
A1
B2
B1
C2
C1
D2
D1
Dh24
Dh25
Dh26
Dh27
Dh28
Dh29
Dh30
Dh31
3V3
XD8
XD9
XD10
XD11
XD12
XD13
XD14
XD15
C218
E2
E1
F2
F1
G2
G1
H2
H1
C 209 C 219
0.1uF 0.1 uF 0.1 uF 0.1uF
C210
XA7
XA8
XA9
XA10
1
2
3
4
1
2
3
4
1
2
3
4
XA11
XA12
XA13
XA14
XA15
XA16
XA17
XA19
1
2
3
4
1
2
3
4
XA18
XA20
XA21
XA22
XA23
XA24
XA25
XA26
1
2
3
4
J2
J1
K2
K1
L2
L1
M2
M1
N2
N1
P2
P1
R2
R1
T2
T1
RN 51
RN 52
RN 48
RN 49
RN 45
RN 46
XD48
XD49
XD50
XD51
XD52
XD53
XD54
XD55
8
7
6
5
2 4.
8
7
6
5
2 4.
XAt11
XAt12
XAt13
XAt14
XAt7
XAt8
XAt9
XAt10
XAt15
XAt16
XAt17
XAt19
XAt23
XAt24
XAt25
XAt26
XAt18
XAt20
XAt21
XAt22
XAt27
XAt28
XAt29
8
7
6
5
2 4.
8
7
6
5
2 4.
8
7
6
5
2 4.
8
7
6
5
2 4.
C203
3V3
XD56
XD57
XD58
XD59
XD60
XD61
XD62
XD63
C212
XA27
XA28
XA29
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B8
2B7
C213
J2
J1
K2
K1
L2
L1
M2
M1
XD24
XD25
XD26
XD27
XD28
XD29
XD30
XD31
XD16
XD17
XD18
XD19
XD20
XD21
XD22
XD23
0.1 uF 0.1uF 0.1uF 0.1uF
C 204
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
N2
N1
P2
P1
R2
R1
T2
T1
C207
3V3
2B1
2B2
2B3
2B4
2B5
2B6
2B8
2B7
C 208 C 216
0.1uF 0.1 uF 0.1 uF 0.1uF
C217
Host Side
3
BW Eb
3,5,8 ,11 DQMh[ 1:7]
5,7
BPOE hb
3,6, 8,11 HC Sb
3,6, 8,11 HB CSb
3,11
CS6hb
3,6
TMSh
3,6 ,13 TC Kh
3
SYS CLK
3,11 ,13 PSDVA Lhb
12, 13 SYS ENb
3,5 ,11 Dh[63: 32]
2
XA t[29:7] 5,6 ,7
XA[29:7] 12
Ds[7:0]
5,8 ,11
5,6,8 ,13 32to6 4ENb
XD[ 63:32]
12
8
8, 11
As[31 :24]
5,8 ,11
2
RAShb
BW Eb
DQ Mh1
DQ Mh2
DQ Mh3
DQ Mh4
DQ Mh5
DQ Mh6
DQ Mh7
PSDVA Lhb
SYS ENb
Dh32
Dh33
Dh34
Dh35
Dh36
Dh37
Dh38
Dh39
Dh40
Dh41
Dh42
Dh43
Dh44
Dh45
Dh46
Dh47
Dh48
Dh49
Dh50
Dh51
Dh52
Dh53
Dh54
Dh55
Dh56
Dh57
Dh58
Dh59
Dh60
Dh61
Dh62
Dh63
Ds0
Ds1
Ds2
Ds3
Ds4
Ds5
Ds6
Ds7
32to6 4ENb
BCTL 1_Outb
BCT L0sb
As24
As25
As26
As27
As28
As29
As30
As31
R 48
6
2
3
4
5
6
8
9
7
1
19
2
5
9
7
4
6
3
8
1
19
D1
D2
D3
D4
D5
D7
D8
D6
U 56
U 48
O1
O2
O3
O4
O5
O7
O8
O6
O1
O4
O8
O6
O3
O5
O2
O7
74LCX541
G1
G2
D1
D4
D8
D6
D3
D5
D2
D7
3V3
74LCX541
G1
G2
OE1
OE2
OE3
OE4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
U 17
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
22
23
24
25
26
27
28
29
32
33
34
35
36
37
38
39
2
3
4
5
6
7
8
9
1
19
2
3
4
5
6
7
8
9
19
1
79
69
59
49
1k
U 42
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
U9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
NC
NC
NC
NC
B1
B2
B3
B4
B5
B6
B7
B8
O1
O2
O3
O4
O5
O6
O7
O8
74LCX245DT
D1
D2
D3
D4
D5
D6
D7
D8
74LCX541
G1
G2
18
17
16
15
14
12
11
13
18
15
11
13
16
14
17
12
78
77
76
75
74
73
72
71
68
67
66
65
64
63
62
61
58
57
56
55
54
53
52
51
48
47
46
45
44
43
42
41
1
11
21
31
1
2
3
4
1
3
4
2
22.
R N43A
R N43B
RN 43C
RN 43D
R N41A
RN 41C
RN 41D
R N41B
8
7
6
5
8
6
5
7
4 3.
R N33A
RN 33D
RN 32D
R N32B
RN 33C
R N32A
R N33B
RN 32C
4 3.
22.
C237
0.1uF
3V3
1
4
4
2
3
1
2
3
C187
0.1uF
3V3
D s32
D s33
D s34
D s35
D s36
D s37
D s38
D s39
D s40
D s41
D s42
D s43
D s44
D s45
D s46
D s47
D s48
D s49
D s50
D s51
D s52
D s53
D s54
D s55
D s56
D s57
D s58
D s59
D s60
D s61
D s62
D s63
BD s0
BD s1
BD s2
BD s3
BD s4
BD s5
BD s6
BD s7
C 19
3V3
BAs 24
BAs 25
BAs 26
BAs 27
BAs 28
BAs 29
BAs 30
BAs 31
0.1uF
3V3
ID TQS34XV245Q3
18
17
16
15
14
13
12
11
18
17
16
15
14
13
12
11
C 89
0.1uF
8
5
5
7
6
8
7
6
XBS0
XBS1
XBS2
XBS3
XBS4
XBS5
XBS6
XBS7
1
C168
XB S[0:7] 12
XGPL2
XH CSb
XHB CSb
XCS6b
XTMS
XTCK
CLKX
XP SDVALb
C170
3V3
Ds[63:3 2] 5,8 ,11
C171
5,9
0.1 uF 0.1uF 0.1uF 0.1uF
C 169
BDs[7:0]
BAs[31 :24] 5,9
Slave Side
MSC8102ADS
Motorola Se miconductor Israel Ltd.
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
Tuesday, Augus
Document Nu mber
t 13, 2002
1
Sh eet
4
BuffersHS, Address Mux
Date:
Size
C
12
12
12
12
12
12
12
12
of
15
PIL OT
R ev
D
C
B
A
Figure 5-9 Schematics. Page 4
80
70
60
50
VCC
VCC
VCC
VCC
GND
GND
GND
GND
10
20
30
40
6, 13 DB UFBENb
BBC TL0
5,8 ,11
As[29 :17]
1k
Slave Side
SN74LVC322 45GKER
SN74LVC322 45GKER
D
C
B
A
32to6 4ENb
5,6, 8,13
R6
5
MSC8102ADSUM/D Ver. 1.2
User’s Manual
118
SN74LVC322 45GKER
SN74LVC322 45GKER
Support Info
D
C
B
A
3,4, 8,11
Dh[63: 0]
DQMh[ 0:7]
3,4, 8,11
3,4, 8,11
4 A[0: 9]
Ah[2 8:18]
8,11 DQMs[0 :3]
8 DQMsm[4: 7]
4,8, 11 Ds[63:0]
3
3
3,4 ,11
DQ Mh0
DQ Mh1
DQ Mh2
DQ Mh3
3
3,4, 11
3, 11
3,4, 8,11
3, 11
8,11
4
8
8
DQM s0
DQM s1
DQM s2
DQM s3
8, 11
5, 11
8, 11
8, 11
8
5
Ah 28
Ah 27
Ah 26
Ah 25
Ah 24
Ah 23
Ah 22
Ah 21
Ah 20
Ah 19
SDA1 0h
Ah 18
BNKh0
BNKh1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
25
26
27
60
61
62
63
64
65
66
24
21
22
23
16
71
28
59
25
26
27
60
61
62
63
64
65
66
24
21
22
23
73
70
69
57
30
14
SYSCLK1-1 68
3V3
67
W Ehb
17
CAShb
18
RAShb
19
SDRMCS hb 20
SDA10s
A11
B NKs0
B NKs1
17
18
19
20
16
71
28
59
WE sb
C ASsb
R ASsb
SDRMCSsb
68
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10(AP)
NC(A11)
BA0
BA1
DQM0
DQM1
DQM2
DQM3
WE
CAS
RAS
CS
CLK
CKE
NC1
NC2
NC3
NC4
NC5
NC6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10(AP)
NC(A11)
BA0
BA1
DQM0
DQM1
DQM2
DQM3
WE
CAS
RAS
CS
CLK
CKE
NC1
NC2
NC3
NC4
NC5
NC6
3V3
SDRAM1-1
MT48LC2M32B2TG -8
3V3
MT48LC2M32B2TG -8
SDRAM2-1
4,8, 11
U 52
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
56
54
53
51
50
48
47
45
31
33
34
36
37
39
40
42
85
83
82
80
79
77
76
74
2
4
5
7
8
10
11
13
Dh24
Dh25
Dh26
Dh27
Dh28
Dh29
Dh30
Dh31
Dh16
Dh17
Dh18
Dh19
Dh20
Dh21
Dh22
Dh23
D h8
D h9
Dh10
Dh11
Dh12
Dh13
Dh14
Dh15
D h0
D h1
D h2
D h3
D h4
D h5
D h6
D h7
56
54
53
51
50
48
47
45
31
33
34
36
37
39
40
42
85
83
82
80
79
77
76
74
2
4
5
7
8
10
11
13
D s24
D s25
D s26
D s27
D s28
D s29
D s30
D s31
D s16
D s17
D s18
D s19
D s20
D s21
D s22
D s23
Ds8
Ds9
D s10
D s11
D s12
D s13
D s14
D s15
Ds0
Ds1
Ds2
Ds3
Ds4
Ds5
Ds6
Ds7
As[29: 19]
U 46
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
Note: The used SDRAM may be changed by the larger
device MT48LC4M32B2TG-7 16Mbyte with identical footprint
73
70
69
57
30
14
67
SYSCLK2-1
3V3
5
4
4
DQ Mh4
DQ Mh5
DQ Mh6
DQ Mh7
3
3
3,4 ,11
3
3,4 ,11
3, 11
3,4,8 ,11
3, 11
Ah 28
Ah 27
Ah 26
Ah 25
Ah 24
Ah 23
Ah 22
Ah 21
Ah 20
Ah 19
SDA1 0h
Ah 18
BNKh0
BNKh1
25
26
27
60
61
62
63
64
65
66
24
21
22
23
17
18
19
20
16
71
28
59
68
68
73
70
69
57
30
14
67
SYSCLK1-2
3V3
25
26
27
60
61
62
63
64
65
66
24
21
22
23
16
71
28
59
W Ehb
CAShb
RAShb
SDRMCS hb
8
WE sb 8,11
17
C ASsb 8,11
18
R ASsb 8,11
19
SDRMCSsb 8,11 20
As28
As27
As26
As25
As24
As23
As22
As21
As20
As19
S DA10s 8, 11
As17 4,8 ,11
B NKs0 8
B NKs1 8
DQMsm4
DQMsm5
DQMsm6
DQMsm7
SYSCLK2-2
32to6 4ENb 4,6, 8,13
67
73
70
69
57
30
14
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10(AP)
NC(A11)
BA0
BA1
DQM0
DQM1
DQM2
DQM3
WE
CAS
RAS
CS
CLK
CKE
NC1
NC2
NC3
NC4
NC5
NC6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10(AP)
NC(A11)
BA0
BA1
DQM0
DQM1
DQM2
DQM3
WE
CAS
RAS
CS
CLK
CKE
NC1
NC2
NC3
NC4
NC5
NC6
3V3
3V3
MT48LC2M32B2TG -8
SDRAM1-2
MT48LC2M32B2TG -8
SDRAM2-2
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
12
32
38
46
84
78
52
6
3
U 51
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
U 44
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
3
2
4
5
7
8
10
11
13
Dh40
Dh41
Dh42
Dh43
Dh44
Dh45
Dh46
Dh47
Dh32
Dh33
Dh34
Dh35
Dh36
Dh37
Dh38
Dh39
4,9 BAs[31: 24]
85
83
82
80
79
77
76
74
D s32
D s33
D s34
D s35
D s36
D s37
D s38
D s39
Dh48
Dh49
Dh50
Dh51
Dh52
Dh53
Dh54
Dh55
2
4
5
7
8
10
11
13
D s40
D s41
D s42
D s43
D s44
D s45
D s46
D s47
31
33
34
36
37
39
40
42
85
83
82
80
79
77
76
74
D s48
D s49
D s50
D s51
D s52
D s53
D s54
D s55
Dh56
Dh57
Dh58
Dh59
Dh60
Dh61
Dh62
Dh63
31
33
34
36
37
39
40
42
D s56
D s57
D s58
D s59
D s60
D s61
D s62
D s63
56
54
53
51
50
48
47
45
56
54
53
51
50
48
47
45
C163
C 33
4,7, 12 BAh 30
2
C 35
3V3
IRQ7 hb
C 197 C37
C 40
C 29
C39
I RQ1sb
C 28
For SDRAM2-1 Device
C 166 C 165 C 21
13
10
9
16
17
48
1
2
3
4
5
6
7
8
18
19
20
21
22
23
24
25
26
28
11
14
15
47
12
U 23
NC1(A21)
A20
FLAS H1
A19
A18
A17
A16
A15
A-1/D15
A14
D14
A13
D13
A12
D12
A11
D11
A10
D10
A9
D9
AM29 LV320DB120
A8
D8
(TC58FVT641)
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
CE
OE
WE
WP/ACC
RY/BY
GND - 26,46
BYTE
VCC - 37
C178
C179
C161
C 153 C 154
C 180 C 181
C182
For SDRAM1-1 Device
RESET
C196
C194
C 22
C151
C152
C150
C 24
13
10
9
16
17
48
1
2
3
4
5
6
7
8
18
19
20
21
22
23
24
25
26
28
11
14
15
47
12
C 38
C195
C 177 C 176
C175
For SDRAM1-2 Device
U 38
C 26
45
43
41
39
36
34
32
30
44
42
40
38
35
33
31
29
3V3
B Dh0
B Dh1
B Dh2
B Dh3
B Dh4
B Dh5
B Dh6
B Dh7
B Dh8
B Dh9
BDh10
BDh11
BDh12
BDh13
BDh14
BDh15
0.1uF
C184
C 223
C183
C174
45
43
41
39
36
34
32
30
44
42
40
38
35
33
31
29
C 16
C167
0.1uF
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
BD s0
BD s1
BD s2
BD s3
BD s4
BD s5
BD s6
BD s7
Tuesday, Augus
Document Nu mber
t 13, 2002
1
1
BDh[15: 0] 4,6 ,7
4,9
Host Side
BDs[7:0]
Slave Side
Sh eet
5
of
SDRAM & Flash for Host/Slave Sides
Date:
Size
C
MSC8102ADS
Motorola Se miconductor Israel Ltd.
NC1(A21)
A20
A19
FLAS H2
A18
A17
A16
A15
A-1/D15
A14
D14
A13
D13
A12
D12
A11
D11
A10
D10
A9
D9
AM29 LV320DB120
A8
D8
(TC58FVT641)
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
CE
OE
WE
WP/ACC
RY/BY
GND - 26,46
BYTE
VCC - 37
RESET
C20
C25
3V3
0.1 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1uF
C172
0.1 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1uF
XAt9
XAt10
XAt11
XAt12
XAt13
XAt14
XAt15
XAt16
XAt17
XAt18
XAt19
XAt20
XAt21
XAt22
XAt23
XAt24
XAt25
XAt26
XAt27
XAt28
XAt29
6,11
F CShb
4,7
BPO Ehb
4,7
BWE0hb
6
BOOTPhb
3,1 1,13 IRQ7 hb
C 36
3,6,1 1,15 PR STb
3V3
C 173
BAs 31
A s9
As10
As11
As12
As13
As14
As15
As16
As17
As18
As19
As20
As21
As22
As23
BAs 24
BAs 25
BAs 26
BAs 27
BAs 28
BAs 29
BAs 30
8, 11
FC Ssb
8,9 (POEs) GPL2s
8
WE 0sb
6
BOO TPsb
8,11 ,13 I RQ1sb
C 34
6,8,11 ,12,15 PRS Tsb
C162
0.1uF 0.1uF 0.1 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1uF 0.1uF 0.1uF
C 32
4,8 ,11 As[9:2 3]
4,6 ,7 XA t[29:9]
3V3
C 30
C164
0.1uF 0.1uF 0.1 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1uF 0.1uF 0.1uF 0.1uF
For SDRAM2-2 Device
2
15
PIL OT
R ev
D
C
B
A
119
MSC8102ADSUM/D Ver. 1.2
User’s Manual
3
9
81
75
55
41
49
35
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
1
15
43
29
Vdd
Vdd
Vdd
Vdd
Vss
Vss
Vss
Vss
44
58
72
86
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
12
32
38
46
84
78
52
6
3
9
81
75
55
41
49
35
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
1
15
43
29
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
12
32
38
46
84
78
52
6
3
9
81
75
55
41
49
35
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
12
32
38
46
84
78
52
6
Vdd
Vdd
Vdd
Vdd
Vss
Vss
Vss
Vss
44
58
72
86
3
9
81
75
55
41
49
35
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
1
15
43
29
Vdd
Vdd
Vdd
Vdd
Vss
Vss
Vss
Vss
44
58
72
86
1
15
43
29
Vdd
Vdd
Vdd
Vdd
Vss
Vss
Vss
Vss
44
58
72
86
Figure 5-10 Schematics. Page 5
Support Info
D
C
B
A
3
3V3
TDIh
TDO hc
TCK hc
10
TDIsc
TDOsc
TCKsc
R 107 10
3V3
R111
5
P14
2
4
6
8
10
12
14
OnCE-SYS
R105
22 .1
P15
TDI
TDO
TCK
NC
,11,12,13
RST
VDD
NC
8
7
6
5
GND
GND
GND
KEY
TMS
NC
TRST
OnCE-SLV
1
3
5
7
HRES EThb 3,11 ,12,13
9
11
13
13
1
3
5
7
HRESE Tsb 8,9,10
9
11
TMSh
TRSThb
TCK hc
SW7
JTAG CHAIN
1
2
3
4
SW DIP- 4/SM
S W6
SW DIP- 8/SM
16
15
14
13
12
11
10
9
CFG-H Ctrl
1
2
3
4
5
6
7
8
ON -> MODCKx = 0
SW5
8
7
6
5
SW Option
1
2
3
4
SW DIP- 4/SM
8
7
6
5
CFG-S Ctrl
SW4
SW DIP- 4/SM
1
2
3
4
P17
1
2
1
2
EE1 Chain
5
No pin (KEY)
TMSh
TRSThb
TMSsc
TRS Tscb
3,4
3,1 2,13
MODCK2s
MODCK1s
DSI 2SYS
D BGs_ENb
SWO PT0
SWO PT1
SWO PT2
H EE1
MODCK 3h
MODCK 2h
MODCK 1h
MODCK 6h
MODCK 5h
MODCK 4h
FC FG_ENb
DBGh_ENb
Cha inSel1
Cha inSel2
SY S64
3,4 ,13
TRSThb
TC Kh
TMSh
2
4
6
8 No pin (KEY)
10
12
14
TP55
Cha inSel1
Cha inSel2
SY S64
MODC K3h
MODC K2h
MODC K1h
MODC K6h
MODC K5h
MODC K4h
FC FG_ENb
DBGh_E Nb
SWOP T0
SWOP T1
SWOP T2
H EE1
MODCK2s
MODCK1s
DSI 2SYS
D BGs_ENb
EE 1in
EE1 out
TD Oi
TD Oh
4
0
R110
1k
0
2
3
5
6
11
10
14
13
U 47
1A
1B
2A
2B
3A
3B
4A
4B
A/B
G
S0
S1
I0A
I1A
I2A
I3A
I0B
I1B
I2B
I3B
U 49
1Y
2Y
3Y
4Y
ZA
ZB
4
7
9
12
7
9
IDT74 CBTLV3257PG
1
15
10
11
12
13
6
5
4
3
14
2
OEB
OEA
IDT74 CBTLV3253PG
15
1
Action
Abo rt-h
HardRst -h
So ftRst-h
Abor t-s
HardRst-s
Sof tRst-s
R 104
7,9
7
22 .1
TDOs
TDO hc
STBUF ENb
TCLK
TCLK
TDOA TM
TMS
TMS
TDIBCSR
Short JTAG chai n
via 8101 and 81 02
0
Long JTAG chai n
via off-boa rd
devices
HardRs t-h
S oftRst-h
Abo rt-s
HardRst -s
So ftRst-s
BC ONF0
BC ONF1
BREVN0
BREVN1
BREVN2
Separate JTAG acce ss
1
1
4
4
BC ONF0
BC ONF1
B REVN0
B REVN1
B REVN2
1
13
13
13
13
13
Not supported
3
3
4
4
BROWN
3
R ED
3
3
BROWN
4
Ab ort-h
1
R ED
BROWN
2
1
S W10
1
3
2
2
2
2
BROWN
4
2
SW3
S W11
1
1
SW1
1
SW2
1
7,9
0
S W12
ChainSel1 ChainSel2
TMSsc
TMSh
TR STscb
TRSThb
TCKsc
TC Khc
TDIsc
3
Cha inSel1
Cha inSel2
TD Io
TDO sc
12
12
ABORT
HARD
RESET
SOFT
RESET
ABORT
HARD
RESET
SOFT
RESET
4
3
4
5
6
7
2
8
9
1
19
TRSTsb
TMSs
8,11
8,11 ,13
8,13
8,11
3
TDIs
TC Ks
8,11
1
3
5
7
9
TCK
TDO
TMS
NC
TDI
XA t[10:7]
B Dh0
B Dh1
B Dh2
B Dh3
B Dh4
4 ,5
2
4
6
8
10
3
3
3V3
8,9, 12,13
8,9, 12,13
8,9, 12,13
8,9, 12,13
8
9
XAt7
XAt8
XAt9
XAt10
XAt27
XAt28
XAt29
TMS
TCLK
TDIBCSR
TDO ISP
HRST 1b
HRST 2b
HRST 3b
GA0
GA1
GA2
GA3
FC FG_ENb
DBGh_ENb
H EE1
D BGs_ENb
E E1ss
EE 1in
Ab ort-h
Abo rt-s
HardRst -h
So ftRst-h
Sof tRst-s
HardRst-s
MODCK1s
MODCK2s
MODCK 1h
MODCK 2h
MODCK 3h
MODCK 4h
MODCK 5h
MODCK 6h
DSI 2SYS
SY S64
SWO PT0
SWO PT1
SWO PT2
B CSRCLK
EXTCL Kh
B Dh0
B Dh1
B Dh2
B Dh3
B Dh4
B Dh5
B Dh6
B Dh7
3,11
B CSRCSb
3,7 ,11 ATMCSb
3,11
CS0hb
3,4, 8,11 HB CSb
3,4, 8,11 HC Sb
4,8 ,11 BCTL 1sb
5,8 ,11 FC Ssb
4,12
BXBCT L0
4
B WEb
3,5,1 1,15 PR STb
XA t[29:27] 4,5 ,7
3V3
GND
VCC
NC
NC
GND
0.1uF
ISP
P13
C224
17
16
15
14
13
18
12
11
BDh[7: 0]
O2
O3
O4
O5
O6
O1
O7
O8
74LCX541
U 54
4,5 ,7
D2
D3
D4
D5
D6
D1
D7
D8
G1
G2
3
TP51
TP47
GA0
GA1
GA2
GA3
TP50
nHR ST1
nHR ST2
nHR ST3
C200
C 186
U 18
TMS
TCK
TDI
TDO
A7
A8
A9
A10
A27
A28
A29
BCSRCS~
ATMCS~
CS0~
HBCS~
HCS1~
BCTL1_In
nCS0s
W_R~
WE~
RESET~
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
CLK
EXTCLK
2
C185
ABRh~
ABRs~
HardRSTh~
SoftRSTh~
SoftRSTs~
HardRSTs~
MODCK1s_In
MODCK2s_In
MODCK1h_In
MODCK2h_In
MODCK3h_In
MODCKh_H1
MODCKh_H2
MODCKh_H3
DSI/SYS
SYS64
SWOPT0
SWOPT1
SWOPT2
FCFG_EN
HEE0_In
HEE1_In
SEE0_In
SEE1_In
EE1_misc_In
GA0
GA1
GA2
GA3
HRST1_In~
HRST2_In~
HRST3_In~
Input/GCLRn
U 50A
U5 0D
U5 0C
3
11
8
2
C199
3V3
C192
3V3
C190
Altera
CPLD
C 189
EP M3256ATC144-7
HRS T1b
HRS T2b
HRS T3b
C191
C198
FCS~
RS232EN_1_EN~
RS232EN_2_EN~
CODEC_EN~
ATM_RST~
FETH_RST~
FRM_RST~
FRMtoTSI~
FLASH_WPh~
FLASH_WPs~
MODCK1h_Out
MODCK2h_Out
MODCK3h_Out
NMIh~
HRESETh~
SRESETh~
RSTCNFGs
SWTE
DSISYNC
DSI32/64
MODCK1s_Out
MODCK2s_Out
SCNFG
BTMD0
BTMD1
BTMD2
NMIs~
HRESETs~
SRESETs~
PRSTs~
HRST1~
HRST2~
HRST3~
DataBufXEn~
DataBufEn~
StBuf_En~
BCTL1_Out
32to64EN~
SIGNALH0_LED
SIGNALH1_LED
SIGNALS0_LED
SIGNALS1_LED
SEE1_LED
LED_EN~
TEST_EN~
HEE0_Out
HEE1_Out
SEE0_Out
EE1_misc_Out
TEST_SIG1
TEST_SIG2
TEST_SIG3
HRS T1b
HRS T2b
HRS T3b
C188
112
60
113
55
48
62
107
56
84
102
101
108
99
110
79
109
21
74
75
27
97
82
116
49
54
72
78
16
14
87
86
88
81
18
12
19
66
91
122
93
92
121
120
103
111
63
45
46
61
15
90
119
0.1uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1 uF
20
89
4
104
38
37
30
70
138
137
133
10
131
139
143
69
126
8
1
128
71
67
118
65
53
100
106
83
25
41
125
43
35
7
34
36
9
134
136
140
22
23
96
5
141
68
44
31
47
132
142
40
2
42
117
29
6
11
80
32
98
39
28
127
2
12
9
3V3
C193
0.1 uF
R 51
R 52
R136
R140
TP54
43.2
43.2
NMI hb
HRES EThb
SRE SEThb
43 .2
43 .2
NMIsb
HRESE Tsb
SRES ETsb
PRS Tsb
DBUFXE Nb
DB UFBENb
STBUFE Nb
32to6 4ENb
1
F CShb
5, 11
RS232EN _1b 7, 15
RS232EN _2b 10, 15
CO DEC_ENb 10, 15
ATM_RS Tb 7
FETH _RSTb 7
FRM_ RSTb 9
FRM toTSI 9
BO OTPhb 5
BOO TPsb 5
MODCK h1 3,11
BNKSE Lh1 3, 11
BNKSE Lh2 3, 11
NMI hb
3, 13
HRESE Thb 3,11, 12,13
SRE SEThb 3,1 1,13
R STCFGs 8, 11
SWT Ea
8
DSISY NCa 8
DSI64a
8
MODCK1 sa 8
MODCK2 sa 8
CN FGSa 8
BNKSEL s0 8, 11
BNKSEL s1 8
BNKSEL s2 8
NMIsb
8,11 ,12,13
HRESET sb 8,9,10, 11,12,13
SRES ETsb 8,1 1,13
PRS Tsb
5,8,1 1,12,15
15
15
15
15
15
15
DBUFXE Nb 4,13
DB UFBENb 4, 13
STBUFE Nb
BCTL 1_Outb
4
32to6 4ENb 4,5, 8,13
nHRS T1
nHRS T2
nHRS T3
S IGH0LD
S IGH1LD
SIGS0LD
SIGS1LD
EE1sLD
L EDENb
TES Ts
8,10,1 1,12,13
8,10, 11,12
8,12
3,1 1,13
3,1 1,13
8
UA RTRX
HRST 1b
12, 13
12, 13
12, 13
Test Signals
8,10 ,12
UAR TTX
CDA TA
HRST 2b
EE0h
EE0h
EE1h
EE1h
E E0ss
EE1o ut
TP48
5 RN 36D 4
2 2.
7 R N36B 2 TEST_SIG1 TP52
2 2.
6 RN 36C 3 TEST_SIG2 TP49
2 2.
8 R N36A 1 TEST_SIG3 TP53
2 2. (*)
HRS T1b
HRST 3b
of
HRS T2b
Sh eet
6
HRS T3b
Motorola Se miconductor Israel Ltd.
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
1
BCSR & JTAG
MSC8102ADS
Tuesday, Augus
Document Nu mber
t 13, 2002
Date:
Size
C
15
PIL OT
R ev
D
C
B
A
Figure 5-11 Schematics. Page 6
130
58
123
51
VCCINT
VCCINT
VCCINT
VCCINT
95
50
76
115
24
73
144
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
124
57
77
52
33
26
17
13
3
64
105
135
129
GND
GND
GND
GND
59
94
114
85
MSC8102ADSUM/D Ver. 1.2
User’s Manual
120
1
13
10
HOST
SLAVE
Support Info
D
C
5
12 L1SY NC
L1 RXD
L1TXD
C265
TP60
TP59
C267
TP61
L4TXD
L4RXD
L3RXD
L3TXD
L2RXD
L2TXD
R194
220
0.01 uF
R189
49 .9
T11
V10
U10
W9
U9
V8
T9
U8
W8
W3
M7
T4
W2
R5
T3
U1
R3
P4
P2
N2
M6
L1
K1
J1
J7
G1
R4
U2
P5
T1
T2
V1
P3
N3
M3
M1
L2
K4
H1
H4
U 26B
158
CPM
0.1uF
F1
11
11
R168
22 .1
ATM Framer
PM5 384-NI
L4CLK
FETH MDIO
FETHM DC
SC C1DSRb
SCC1C TSb
12
L3CLK 12
AT MFCLK
L2CLK 12
FETHTXCK
FETH RXCK
C LK2
12
L1CLK 12
ATMTXP RTY
ATMRXPRTY
SCC1R TSb
SC C1TXD
SCC1R XD
3
FETHTXCK
FE THTXD[0:3]
FETHTXEN
FETHTXER
FETH RXCK
U 22
R156
R162
H10
H11
H14
G10
G11
L12
L13
M13
M14
P13
P12
L11
M11
N11
P11
K10
L10
P10
J9
K9
L9
J11
J10
K11
J14
G14
F9
F10
F11
E12
E13
D9
C9
B9
A9
D10
A10
C11
B11
A11
B12
A12
A13
A14
B13
B14
C14
E9
E14
E10
C13
F14
22.1
FETHTXD0
FETHTXD1
FETHTXD2
FETHTXD3
22.1
25
30
31
32
33
35
34
29
37
38
15
16
17
12
13
14
21
20
19
18
FETH
FETH
FETH
FETH
3
ATMTXD7
ATMTXD6
ATMTXD5
ATMTXD4
ATMTXD3
ATMTXD2
ATMTXD1
ATMTXD0
ATMRX D7
ATMRX D6
ATMRX D5
ATMRX D4
ATMRX D3
ATMRX D2
ATMRX D1
ATMRX D0
GND
MI31 00HAH-25.000MHz
2
OUT
VCC
4
3V3
FETHRX D[0:3]
F ETHCRS
FETH RXDV
FETH RXER
FETHM DC
FETHM DIO
FETHCOL
1
6 FETH _RSTb
1k
R137
EN
RXD0
RXD1
RXD2
RXD3
U 25
TX_CLK
TXD0
TXD1
TXD2
TXD3
TX_EN
TX_ER
RX_CLK
RXD0
RXD1
RXD2
RXD3
CRS
RX_DV
RX_ER
MDC
MDIO
COL
RESET
OSCIN
Ether net PHY
ATMRXPRTY
ATM RSOC
AT MRCA
ATMRXE Nb
AT MFCLK
TPOTPI+
TPI-
RX_EN
ANEG
SPEED
DPLX
RPTR
L_LED
FD_LED
C_LED
LA_LED
REXT
NQ80 225
43
44
2
3
26
40
11
42
23
5
6
7
8
39
C232
R 157
49 .9
2
R166
49 .9
TPO-
TPO+
TPI+
C248
R158
24 .9
11
11
11
11
11
11
11
11
3V3
R165
R144
R164
R145
R146
R163
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
3V3
C115
0.1 uF
C114
0.1 uF
1 0k
R142
R169
R143
R 83
C 43
(*)
10pF -2KV
U 24
6
7
2
6
RR
TR
1
3
8
10
2
9
11
1
V-
V+
VCC
U 12
R1IN
R2IN
R3IN
R4IN
R5IN
4
5
6
7
8
9
10
11
3
27
26
C 46
(*)
R173
75
C 41
D SR
D TR
R TS
TXD
C TS
RXD
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tuesday, Augus
Document Nu mber
L R1
R167
75
1
L R2
11
10
3V3
G
R
RJ45 SHLD
P20
10/100M ETH
1
2
3
4
5
6
7
8
C 47
(*)
1
6
2
7
3
8
4
9
5
P8
RS232-1
TDM1-4 ports may be available
when MII set disable
0.1uF
C128
0.1uF
C113
0.1uF
C127
LA
Connec tor
TDM
Resistors R170,R175, R178,R179
set address of MII.
Not assembled by default.
Address of MII port is "0"
1nF- 2KV
R 174
75
14
R160
75
15
100M
16
TG1 10-S050N2
LD13
R176
330
FD
C 42
(*)
10pF -2KV
R180
330
LED_COL
R177
330
R175
47. 5k
(*)
LD14
R151
330
R179
47.5k
(*)
PortC2
PortB2
R178
47. 5k
(*)
L2T XD 12
L2SY NC 12
L2 RXD 12
L3T XD 12
L3SY NC 12
L3 RXD 12
PortD2
11
11
11
11
11
RS-232
L4T XD 12
L4SY NC 12
L4 RXD 12
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
EN
DGND
10pF -2KV
t 13, 2002
1
Sh eet
7
of
Host Processor-Part II, Host Comminication
Date:
Size
C
Tit le
10pF -2KV
MSC8102ADS
Motorola Se miconductor Israel Ltd.
MAX3241ECAI
R1OUTB
R2OUTB
T1IN
T2IN
T3IN
C2-
C2+
C1-
C1+
SHDN
SCC1RT Sb
SC C1TXD
SCC1RXD
SCC1CT Sb
SC C1DSRb
22
28
24
1
2
14
13
12
21
20
19
18
17
16
15
25
23
T1OUT
T2OUT
T3OUT
R170
47.5k
(*)
0.01 uF LED_LINK
R172
24 .9
TPI-
3V3
R 171
24 .9
R159
24 .9
3V3
C 247 C 234
1 0k
C253
R147
C228
FETHCOL
FETHTXD2
F ETHCRS
FETHTXER
FETHTXEN
FETH RXDV
FETHTXD0
FETH RXD1
FETHTXD1
SCC1RT Sb
SC C1TXD
SCC1R XD
SCC1CT Sb
SC C1DSRb
2
LA Conne ctor
ATM ERCA
ATM RSOC
ATMRXENb
ATMRXPRTY
ATMTXP RTY
ATMTC Ab
ATMTS OC
ATM TXENb
6, 15 RS232E N_1b
SCC1C TSb
SCC1R XD
SC C1DSRb
SCC1R TSb
SC C1TXD
0.1 uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1 uF
C 240
ATMRXD[0:7]
ATMTXD[0 :7]
ATMTXP RTY
ATMTS OC
ATMTC Ab
ATM TXENb
AT MFCLK
AT MFCLK 11
AT MRCA
ATM RSOC
ATMRXENb
ATMRXPRTY
ATMTX PRTY
ATMTC Ab
ATMTSOC
ATM TXENb
TPO+
PHY Power-up setting :
100 Mbps Selected, AutoNegotiation Enabled, Full Duplex
C222
0.1uF
0
R197
RADR4
RADR3
RADR2
RADR1
RADR0
RDAT15
RDAT14
RDAT13
RDAT12
RDAT11
RDAT10
RDAT9
RDAT8
RDAT7
RDAT6
RDAT5
RDAT4
RDAT3
RDAT2
RDAT1
RDAT0
RPRTY
RSOC/RSOP
RCA/RPA
RENB
RFCLK
TADR4
TADR3
TADR2
TADR1
TADR0
TDAT15
TDAT14
TDAT13
TDAT12
TDAT11
TDAT10
TDAT9
TDAT8
TDAT7
TDAT6
TDAT5
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
TPRTY
TSOC/TSOP
TCA/PTPA
TENB
TFCLK
3
Note :
Set bit ATM8 f or 8-bit
UTOPIA Level 2 Mode
LED_LINK
4
V9
R1
N5
P1
N1
M2
L7
L3
K3
J3
H3
V4
T5
T6
V3
P10
PC4/Rx/L1ST4/CD
W10
PC5/Tx/L1ST3/CTS
N10
PC6/L1ST2/CD/RxAddr[2]/ RxClav1
T10
PC7/L1ST1/CTS/TxADDR[2]/TxClav1
PC12/L1ST3/CD/RENA/RxADDR[1]
PC13/L1ST4/CTS/CLSN/TxADDR[1]
PC14/L1ST2/CD/ENA/RxADDR[0]
PC15/SMTXD/CTS/CLSN/TxADDR[0]
PD7/SMSYN/TxAddr[3]/TxClav2
REFCLK
TDO
TDI
TRST
TCK
TMS
ALE
CS
RD
WR
RST
INT
SDTTL
APSO-
APSO+
APSI-
APSI+
APECLV
SPECLV
SD
RXD+
RXD-
TXD-
TXD+
U30A
K2
PD29/RTS/TENA/RxAddr[3]/ RxClav2
J2
PD30/TXD/DRACK/DONE
H2
PD31/RXD/DRACK/DONE
U4
PD16/TxPrty/SPIMISO
N7
PD17/BRGO/RxPrty/SPIMOSI
U3
PD18/RxAddr[4]/ RxClav3/SPICLK
V2
PD19/TxAddr[4] /TxClav3/BRGO/SPISEL
C 49
F2
M2
L3
L4
M3
L2
A4
A2
A3
B2
B3
C3
E4
D2
D1
J2
J1
J5
J6
H3
H1
H2
0.1uF
3V3
0
R 192
R202
0 (*)
10k
158
PC22/L1ST1/CLK10/DREQ
PC23/CLK9/DACK
PC24/BRGO/CLK8/TIN3/TOUT/DREQ
PC25/BRGO/CLK7/TIN4/DACK
PC26/BRGO/CLK6/TOUT/TMCLK
PC27/BRGO/CLK5/TGATE2
PC28/BRGO/CLK4/TIN1/TOUT/CTS/CLSN
PC29/BRGO/CLK3/TIN2/CTS/CLSN
PC30/BRGO/CLK2/TOUT
PC31/BRGO/CLK1/TGATE1
MSC8101
PA6/L1RSYNC
PA7/SMSYN/L1TSYNC/GRANT
PA8/SMRxD/L1RxD[0]/L1RxD
PA9/SMTxD/L1TxD[0]
PA10/RxD[0]/MSNUM[5]
PA11/RxD[1]/MSNUM[4]
PA12/RxD[2]/MSNUM[3]
PA13/RxD[3]/MSNUM[2]
PA14/RxD[4]/RxD[3]
PA15/RxD[5]/RxD[2]
PA16/RxD[6]/RxD[1]
PA17/RxD[7]/RxD[0]/RxD
PA18/TxD[7]/TxD[0]/TxD
PA19/TxD[6]/TxD[1]
PA20/TxD[5]/TxD[2]
PA21/TxD[4]/TxD[3]
PA22/TxD[3]
PA23/TxD[2]
PA24/TxD[1]/MSNUM[1]
PA25/TxD[0]/MSNUM[0]
PA26/RxClav/RX_ER
PA27/RxSOC/RX_DV
PA28/RxEn/TX_EN
PA29/TxSOC/TX_ER
PA30/TxClav/RTS/CRS
PA31/TxEn/COL
IRQ6 hb
6,9
TCLK
6,9 TMS
C 50
PB18/RxD[3]/I2CSCL
PB19/RxD[2]/I2CSDA
PB20/RxD[1]/L1TXD[1]/L1RSYNC
PB21/RxD[0]/RxD/L1TXD[2]/L1TSYNC/GRANT
PB22/TxD[0]/TxD/L1RXD[1]/L1RXD
PB23/TxD[1]/L1RxD[2]/L1TxD
PB24/TxD[2]/L1RxD[3]/L1RSYNC
PB25/TxD[3]/L1TxD[3]/L1TSYNC/GRANT
PB26/CRS/L1RxD
PB27/COL/L1TxD
PB28/RTS/Rx_ER/TENA/L1TSYNC/GRANT
PB29/Tx_EN/L1RSYNC
PB30/TxD/Rx/DV/L1RxD
PB31/Tx_ER/RxD/L1TxD
330
R193
R188
49.9
R201
(*) 0
K1
UTO PIA mode only
11
12
12
ATMRX D0 12
ATMRX D1
ATMRX D2
ATMRX D3
ATMRX D4
ATMRX D5
ATMRX D6
ATMRX D7
ATMTXD7
ATMTXD6
ATMTXD5
ATMTXD4
ATMTXD3
ATMTXD2
ATMTXD1
ATMTXD0
L3
AT MRCA
ATM RSOC
ATMRXENb
ATMTSOC
ATMTC Ab
ATM TXENb
FETHCRS
FETHC OL
FETH RXER
FETHTXEN
FETH RXDV
FETHTXER
FETH RXD3
FETH RXD2
FETH RXD1
FETH RXD0
FETHTXD0
FETHTXD1
FETHTXD2
FETHTXD3
3V3
L2
U 28
0.1uF
TDOTSI
SD
Rx D+
Rx D-
50OHM
R185
3V3
T xD+
9
6 TDO ATM
R186
8
3
3,6 ,11 ATMCSb
4,5
BPOE hb
4,5
BWE0hb
6
ATM_RS Tb
3, 13 IRQ6 hb
R187
GND
OUT
VCC
4
Tx D-
3V3
150R199
7
4
2
3
U 29
EN
Only one of two re sistors
*R201, *R202 may be placed
for JTAG chain conf iguration
4
LED_COL
13
14
15
16
9
10
11 AT MRXD[0:7]
AT MRXD[0:7]
ATMTXD[0 :7]
11 ATMTXD[0 :7]
+ C 48
C260
0.1uF
TXDP
TXDN
SD
RXDP
RXDN
1k
R205
1
2
4,5 ,6 XAt [29:23]
4,5 ,12 BAh[3 1:30]
4,5 ,6 BDh[7: 0]
L ED GREEN
XR JM-S-01-8-8-W11
15
PIL OT
R ev
D
C
B
A
121
MSC8102ADSUM/D Ver. 1.2
User’s Manual
L ED GREEN
1
10
24
28
VDD1
VDD2
VDD3
VDD4
GND1
GND2
GND3
GND4
GND5
GND6
4
9
22
27
36
41
FETHRX D[0:3]
FE THTXD[0:3]
C259
0.1uF 10uF
Led
Photodiode
HFBR-58 05
0.1uF
150R198
1
2
CHASIS
C 284
MI310 10HAH-19.44MHz
5
F7
TSEN
L5
M5
K6
L6
P4
P2
P3
TPOH
TPOHEN
TPOHFP
TPOHCLK
RPOH
RPOHFP
RPOHCLK
G9
XOFF
RVAL
RMOD
REOP
RERR
L14
K14
J12
J13
POS_ATM
J8
STPA
TMOD
TEOP
TERR
E11
D11
D14
C12
L8
K8
L7
K7
P6
N5
P5
TTOH
TTOHEN
TTOHFP
TTOHCLK
RTOH
RTOHCLK
RTOHFP
M1
N1
N2
P1
TDCC
TDCLK
RDCC
RDCLK
D7
D6
D5
D4
D3
D2
D1
D0
ATMT CLK
AT MRCLK
E7
D7
C7
B7
A7
E8
D8
A8
TX_GND
RX_GND
9
1
L1
N9
P9
TFPI
TFPO
TCLK
B Dh0
B Dh1
B Dh2
B Dh3
B Dh4
B Dh5
B Dh6
B Dh7
150R200
1
2
5
RX_VCC
1
2
6
TX_VCC
CHASSIS1
CHASSIS2
10
11
P7
M9
P8
RALRM
RFPO
RCLK
A5
B5
C5
D5
E5
A6
D6
E6
F6
A9
D4
A8
A7
A6
A5
A4
A3
A2
A1
A0
XAt23
XAt24
XAt25
XAt26
XAt27
XAt28
XAt29
BA h30
BA h31
B
A
155M ATM
Figure 5-12 Schematics. Page 7
Support Info
6, 11
11, 13,15 D BBsb
(INT_OUTb)
3,1 1,13 IRQ1 hb
5,1 1,13 IRQ1sb
6,11 ,12,13 NMI sb
11 ,13 TAsb
11 ,13 TEAsb
11 TBSTsb
11 TSsb
11 TSIZ s0
11 TSIZ s1
11 TSIZ s2
11 TSIZ s3
PSD QM0
BNKSELs[ 0:2]
DQMs[1 :3]
DQMs[4 :7]
PSDVAL sb
5
D BBsb
D REQ1sb
D REQ2sb
D REQ3sb
D REQ4sb
R 55
TP14
TP27
TP24
TP26
TP25
TP28
TP30
TP29
TP31
TP33
TP32
IRQ1hb
I RQ1sb
NMIsb
TAsb
TE Asb
0
CLKIN
(*)
TP17
22 .1
22 .1
0
R 40
R 53
22 .1
22 .1
(*)
3V3
R 50
R 43
R 91
R 44
0
R 41
ABBsb
AACKsb
NMI_OUT
RSTCONF
SRESET
HRESET
PORESET
EE0
EE1
TCK
TDI
TDO
TMS
TRST
BCTL0
BCTL1/CS5
PGTA/PPBS/PUPMWAIT/PGPL4
POE/PSDRAS/PGPL2
PSDA10/PGPL0
PSDAMUX/PGPL5
PSDCAS/PGPL3
PSDVAL
PSDWE/PGPL1
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE/PSDDQM/PBS/HWBS/HDBS[4]
PWE/PSDDQM/PBS/HWBS/HDBS[5]
PWE/PSDDQM/PBS/HWBS/HDBS[6]
PWE/PSDDQM/PBS/HWBS/HDBS[7]
BNKSEL0/BM0/TC0
BNKSEL1/BM1/TC1
BNKSEL2/BM2/TC2
DBG
DBB/IRQ5
BG
BR
DP0/DREQ1/EXT_BR2
DP1/DACK1/EXT_BG2/IRQ1
DP2/DACK2/EXT_DBG2/IRQ2
DP3/DREQ2/EXT_BR3/IRQ3
DP4/DACK3/EXT_BG3/IRQ4
DP5/DACK4/EXT_DBG3/IRQ5
DP6/DREQ3/IRQ6
DP7/DREQ4/IRQ7
INT_OUT/IRQ7
GBL/IRQ1
NMI
TA
TEA
TBST
TS
TSIZ0
TSIZ1
TSIZ2
TSIZ3
U7A
J12
H13
N16
P16
P19
T18
R19
R17
T17
T16
R16
R15
G14
R10
F4
P15
P17
T10
R18
T8
R8
T9
R9
G11
H10
J11
G7
K6
N6
K5
R7
T7
R6
T6
H8
K7
J17
J7
H7
P18
N19
G18
J18
E2
D2
C4
E4
E3
0
TP16
4 RN1 5D 5
22. 2 R N15B 7
3 RN1 5C 6 22.
22. 3 RN 17C 6
4 RN1 7D 5 22.
22. 2 R N17B 7
1 R N17A 8 22.
22.
UPMW AITsb
BNKSEL s0
BNKSEL s1
BNKSEL s2
DQM s1
DQM s2
DQM s3
DQM s4
DQM s5
DQM s6
DQM s7
GPL_C AS
TP15
GPL_R AS
GPL_SD A10
GPL_WE
R 68
D3
D4
TCKs
EE0s
EE1s
TRSTsb
B6
F3
C5
E5
F2
J10
IRQ5hb
CL OCKs
SRES ETsb
HRESE Tsb
PRS Tsb
2
J P4
11,1 2,13
EX CLKs 11
BNKSEL s2
BNKSEL s1
EE0s
EE0s
TP9
TP10
F R3
10k
R 92
0
(*)
B NK0
B NKs0
B NKs1
B NK1
CLKOU Ts
11
5
5
11
C 23
1
C146
4
13
8
9
1
5
12
4
MSC8102
SYSTEM
MSC8102
Bottom Vi ew
FCPBGA 20x20 431pins
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
ART RY
2
0.01 uF
10uF
11
11
11 ,13
9,1 1,13
9,1 1,13
16
6
7
10
11
2
3
14
15
TP4
0
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
I RQ5sb
I RQ2sb
I RQ3sb
AR TRYsb
D LLINs
CLKS1
CLKS2
5
5
4, 12
AR TRYsb 11 ,13
11
11
SYSCLK2-1
SYSCLK2-2
For signal SYSCLK2-1 ,
SYSCLK2-2 & DLLI Ns
keep trace lengths equ al
0
R 26
BA DDR27s
BA DDR28s
IRQ5sb
IRQ2sb
IRQ3sb
R 27
(*)
CLKOUT
CLKB1
CLKB2
CLKB3
CLKB4
CLKA1
CLKA2
CLKA3
CLKA4
PLL CLK-DRIVER
U 43
VCC1
VCC2
S2
S1
REF
GND1
GND2
3
IRQ15/TDM0RCLK
TDM0RDAT
IRQ14/TDM0RSYN
DRACK2/DONE2/TDM0TCLK
IRQ13/TDM0TDAT
TDM0TSYN
DACK2/TDM1RCLK
TDM1RDAT
DREQ2/TDM1RSYN
DRACK1/DONE1/TDM1TCLK
DACK1/TDM1TDAT
DREQ1/TDM1TSYN
IRQ11/TDM2RCLK
IRQ12/TDM2RDAT
IRQ10/TDM2RSYN
IRQ8/TDM2TCLK
IRQ9/TDM2TDAT
IRQ7/TDM2TSYN
IRQ5/TDM3RCLK
IRQ6/TDM3RDAT
IRQ4/TDM3RSYN
IRQ2/TDM3TCLK
IRQ3/TDM3TDAT
IRQ1/TDM3TSYN
TTs[0:4] 11
J21
N20
H18
G22
J19
H19
F22
F17
F18
F19
G21
G19
E20
F21
E22
E21
F20
E19
C19
D22
C22
D19
C21
C20
C16
D16
E6
C6
K14
H6
K9
Ds[63:0]
4,5 ,11
Socket 3M 432pin
243 1-9035-01-2501
TESTs
Socket/Ad apter System
FJS43 1-700G
Adapter A dv.Tech.
2
5
11
14
3
6
10
13
4
7
9
12
1Y
2Y
3Y
4Y
4
7
9
12
2
3,4, 11 Ah[10 :7]
6,9,1 2,13 GA[0: 3]
Dh31
Dh30
Dh29
Dh28
Dh27
Dh26
Dh25
Dh24
Dh23
Dh22
Dh21
Dh20
Dh19
Dh18
Dh17
Dh16
Dh15
Dh14
Dh13
Dh12
Dh11
Dh10
D h9
D h8
D h7
D h6
H D5
H D4
H D3
H D2
H D1
H D0
H D[5:0]
M3
N3
N4
M2
P3
N2
P4
N5
P5
R5
T3
P2
U3
R2
T2
U2
Y3
AA3
AB3
AA4
AB4
AA5
Y5
AB5
Y2
W2
W3
W4
V2
U4
T4
T5
HD31
HD30
HD29
HD28
HD27
HD26
HD25
HD24
HD23
HD22
HD21
HD20
HD19
HD18
HD17
HD16
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
HD7
HD6
HD5/CNFGS
HD4/MODCK2
HD3/MODCK1
HD2/DSI64
HD1/DSISYNC
HD0/SWTE
DQ Mh0
DQ Mh1
DQ Mh2
DQ Mh3
U 41
1A
2A
3A
4A
1B
2B
3B
4B
A/B
G
1Y
2Y
3Y
4Y
DSI
MSC8102
1
15
2
5
11
14
3
6
10
13
UPMW AIThb
DQ Mh4
DQ Mh5
DQ Mh6
DQ Mh7
DQMsm4
DQMsm5
DQMsm6
DQMsm7
4
7
9
12
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
U7B
HA29
HA28
HA27
HA26
HA25
HA24
HA23
HA22
HA21
HA20
HA19
HA18
HA17
HA16
HA15
HA14
HA13
HA12
HA11
DQM s4
DQM s5
DQM s6
DQM s7
6
7
7
6
4
3
1
2
4
3
Tuesday, Augus
Document Nu mber
F5
H3
G3
J3
G4
G2
G5
F6
K3
H2
H5
J2
G6
K4
K2
L3
J5
L2
L4
1
1
5, 11
Ah 29
Ah 28
Ah 27
Ah 26
Ah 25
Ah 24
Ah 23
Ah 22
Ah 21
Ah 20
Ah 19
Ah 18
Ah 17
Ah 16
Ah 15
Ah 14
Ah 13
Ah 12
Ah 11
5,11
9
8
DQMs[4 :7] 11
SDA10s
5,11
9
GPL0s
GPL1s
WE sb
9
5,11
5,11
5 ,9
R ASsb
GPL3s
5
GPL2s
DQMs0
C ASsb
W E0sb
Sh eet
MSC8102 - Part I
t 13, 2002
Date:
Size
C
MSC8102ADS
Motorola Se miconductor Israel Ltd.
3 RN1 4C
22.
2 RN 14B
22.
2 RN 16B
22.
3 RN1 6C
22.
5 RN1 3D
22.
6 RN1 3C
22.
8 RN 11A
22.
7 RN 11B
22.
5 RN1 1D
22.
6 RN1 1C
22.
IDT74 CBTLV3257PG
PSD QM0
GPL_C AS
GPL_R AS
GPL_WE
GPL_SD A10
32to6 4ENb
R1
1k
(GPL2)
(CS3)
(CS4)
10, 12
CC LK
11, 12 TIMER0
11, 12 TIMER1
6,1 0,12 CDA TA
H BCSb
HC Sb
UPM WAIThb
RAShb
3,4, 5,11 DQMh[ 0:3]
3,4,6 ,11
3,4,6 ,11
3,11 ,13
3,4, 5,11
H D4
H D5
H D3
H D2
H D1
H D0
5 DQMsm[4: 7]
4,5, 6,13 32to6 4ENb
3,4, 5,11 DQMh[ 4:7]
HD[5:0]
3,4, 5,11 Dh[31 :0]
9,11 ,12,13
9,1 1,12
9,11 ,12,13
9,1 1,12
9,11 ,12,13
9,11 ,12
9,1 1,12
9,1 1,12
9,1 1,12
9,1 1,12
9,1 1,12
9,11 ,12
9,11 ,12,13
9,11 ,12,13
9,11 ,12,13
9,11 ,12,13
9,11 ,12,13
9,11, 12,13
9,11 ,12,13
9,11 ,12,13
9,11 ,12,13
9,11 ,12,13
9,11 ,12,13
9,11, 12,13
1Y
2Y
3Y
4Y
11 ,12
10,1 1,12
6,10, 11,12
6,10,1 1,12,13
U 40
1A
2A
3A
4A
1B
2B
3B
4B
A/B
G
R 79
1k
U 39
1A
2A
3A
4A
1B
2B
3B
4B
A/B
G
IDT74 CBTLV3257PG
1
15
2
5
11
14
3
6
10
13
IDT74 CBTLV3257PG
1
15
available
FJA431- 702GG
Socket Adv.T ech.
TD _B0
R D_A0
R D_B0
TD MCLK0
TD _A0
TDMSY N0
TD _B1
R D_A1
R D_B1
TD MCLK1
TD _A1
TDMSY N1
TD _B2
R D_A2
R D_B2
TD MCLK2
TD _A2
TDMSY N2
TD _B3
R D_A3
R D_B3
TD MCLK3
TD _A3
TDMSY N3
D h3
D h2
D h1
D h0
4 .7k 4 .7k 4.7k 4.7k
4.7k 4.7k
D h4
D h5
5, 11
11
5,11
9,11
9, 11
CLKOU Ts
TIM ER_CLK2
TIMER3
UA RTRX
UAR TTX
FC Ssb
C S1sb
SDRMCSsb
TSI CSb
F ALCCSb
6,12
DL LINs
CLKOUT-S
0
Note: One of these sockets may be
for the MSC8102 chip
IRQ15_ 2sb
IRQ14_ 2sb
1k
R 70
TP13
2sb
2sb
2sb
sb
sb
sb
sb
sb
sb
sb
sb
sb
IRQ13_ 2sb
IRQ11_
IRQ12_
IRQ10_
IRQ8_2
IRQ9_2
IRQ7_2
IRQ5_2
IRQ6_2
IRQ4_2
IRQ2_2
IRQ3_2
IRQ1_2
R 61
R 60
10k
TP42
MODCK1 sa
DSI64a
DSISY NCa
SWT Ea
6
R 80
3,4, 5,11 Dh[3:0]
6
6
6
6
1 R N16A 8
22.
1 RN 14A 8
4 RN1 6D 5 22.
22.4 RN1 4D 5
22.
TEST
DLLIN
CLKOUT
TIMER2/TMCLK/GPIO30
TIMER3/GPIO31
URXD
UTXD
XD[ 5:0]
5
6 MODCK2 sa
6 CN FGSa
3,4, 5,11 Dh[5: 4]
1 nF
TP41
TP40
HR/W
HWBS0/HDBS0
HWBS1/HDBS1
HWBS2/HDBS2
HWBS3/HDBS3
5, 11
11
11
EE0s
EE1s
4,11 BCT L0sb
4,11 BCT L1sb
TCKs
TDIs
TDOs
TMSs
TRSTsb
EXCLK
R 45
11, 13 ABBsb
11, 13 A ACKsb
ART RY
4,5 ,11 As[31: 0]
R 54
R 42
43.2
43 .2
DIP
1k
11,1 2,13
10k
C 15
2
of
PIL OT
R ev
Ah[29 :11]
3,4, 5,11
15
D
C
B
A
Figure 5-13 Schematics. Page 8
HCID0
HCID1
HCID2
HCID3
W11
W10
HDST0
HDST1
GA0
GA1
GA2
GA3
R 17 4 .7k
R 16 4 .7k
R 18 4 .7k
R 15 4.7k
B19
C18
C17
D17
Ah7
Ah8
Ah9
Ah 10
E7
C7
D7
D8
N15
N8
P8
P7
P6
To TSI
To Framer/TSI
GPIO0/CHIP_ID0
TIMER0/CHIP_ID1
TIMER1/CHIP_ID2
GPIO29/CHIP_ID3
HCLKIN
HBRST
HBCS
HCS
HTA
P9
M16
N9
N17
H14
TP22
TP23
6,11 ,13
6,11
6,11
6,11
6,13
6,11 RSTCFGs
6,1 1,13 SRES ETsb
6,9,10 ,11,12,13 HRESE Tsb
5,6,1 1,12,15
PRS Tsb
3,1 1,13 IRQ5 hb
(NMI_OUTsb)
1
49 .9
5
Socket 8P
R 38
EE1s
EE1s
U50B
XD0
SMB Straight
3V3
8
VCC
OUT
GND
4
1k
1k
EE0
Slave
For Cl ock Mode 11
JP2
R 37
PRS Tsb
R128
P2
R 39
*-
*41.6MHz
U5
EXTCLK-S
0.1uF
C 76
E E0ss
1k
5,6,11 ,12,15 PRS Tsb
3
XD1
CS7/TT4
CS6/TT3
CS5/TT2
TT1
TT0
CS4
CS3
CS2
CS1
CS0
H16
J16
K16
T13
R14
H17
L18
K18
G17
N18
TTs4
TTs3
TTs2
TTs1
TTs0
BADDR27
BADDR28
BADDR29/IRQ5
BADDR30/IRQ2
BADDR31/IRQ3
J8
L7
L8
K8
G10
D
6
R 36
C Y2309ZC-1H
4
XD2
R126
XD4
C
B
A
6
6 EE1ss
EE1
*R92 is not as sembled
for PLL function. F or buffer
function it should b e mounted.
XD3
R132
XD5
R 133
TP3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
AA20
AB21
AA21
AA22
Y21
Y22
W22
W21
V19
V20
V21
V22
U21
U22
T22
T21
R22
R20
R21
P22
N22
M22
L22
N21
M21
L21
K20
L20
K22
K21
J22
H22
A s0
A s1
A s2
A s3
A s4
A s5
A s6
A s7
A s8
A s9
As10
As11
As12
As13
As14
As15
As16
As17
As18
As19
As20
As21
As22
As23
As24
As25
As26
As27
As28
As29
As30
As31
1
R127
R 134
Ds0
Ds1
Ds2
Ds3
Ds4
Ds5
Ds6
Ds7
Ds8
Ds9
D s10
D s11
D s12
D s13
D s14
D s15
D s16
D s17
D s18
D s19
D s20
D s21
D s22
D s23
D s24
D s25
D s26
D s27
D s28
D s29
D s30
D s31
D s32
D s33
D s34
D s35
D s36
D s37
D s38
D s39
D s40
D s41
D s42
D s43
D s44
D s45
D s46
D s47
D s48
D s49
D s50
D s51
D s52
D s53
D s54
D s55
D s56
D s57
D s58
D s59
D s60
D s61
D s62
D s63
V5
V6
U5
U6
V7
V8
U7
V9
U8
U9
V10
U10
V11
V12
U11
U12
T12
U13
V13
U14
V14
T14
U15
T15
V16
U16
U17
V17
U18
V18
T19
U19
W18
W16
Y19
AA19
AB20
Y18
AA18
AB19
W14
AB18
AA17
Y14
AB17
AB16
AA15
AB15
AB14
AB13
AB12
Y11
AA11
AB11
AA10
AB10
AB9
AB8
Y8
AA7
Y7
AB7
AB6
AA6
ABB/IRQ4
AACK
ARTRY
ALE
G12
H12
H11
K17
3
1
O SCCLK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
HD_D32
HD_D33
HD_D34
HD_D35
HD_D36
HD_D37
HD_D38
HD_D39
HD_D40
HD_D41
HD_D42
HD_D43
HD_D44
HD_D45
HD_D46
HD_D47
HD_D48
HD_D49
HD_D50
HD_D51
HD_D52
HD_D53
HD_D54
HD_D55
HD_D56
HD_D57
HD_D58
HD_D59
HD_D60
HD_D61
HD_D62
HD_D63
+
MSC8102ADSUM/D Ver. 1.2
User’s Manual
122
JP3
5
4
2
1
2
1
4
5
3
2
Support Info
D
8,11 ,12
8,11 ,12
8,11 ,12
8,11 ,12
4,5
4,5
TD MCLK0
TD MCLK1
TD MCLK2
8,11 ,12,13
TDMSYN0
TDMSYN1
TDMSYN2
8,11 ,12,13
8,11 ,12,13 TD_A3
8,11 ,12,13 R D_A3
BAs[31 :24]
R 49
8 RN 9A
7 RN 9B
6 RN9C
22.
BDs[7:0]
TD_ A3F
1
2
3
5
18
17
16
15
14
13
12
11
3V3
U8
BAs 31
BAs 30
BAs 29
BAs 28
BAs 27
BAs 26
BAs 25
BAs 24
B Ds7
B Ds6
B Ds5
B Ds4
B Ds3
B Ds2
B Ds1
B Ds0
1
19
2
3
4
5
6
7
8
9
1
15
2
3
5
6
11
10
14
13
U 11
D1
D2
D3
D4
D5
D6
D7
D8
G1
G2
A/B
G
1A
1B
2A
2B
3A
3B
4A
4B
U 10
74LCX541
4Y
3Y
2Y
1Y
O1
O2
O3
O4
O5
O6
O7
O8
C 88
0.1uF
4
7
9
12
1Y
2Y
3Y
1A
1B
2A
2B
3A
3B
4A
4B
2
3
5
6
11
10
14
13
IDT74 CBTLV3257PG
9
7
22 .1 4
4Y
C 18
T_ CLK
T_ SYNC
CLK MST
0.1uF
0.1uF
1k
R 97
C155
3V3
1
8,11 ,12,13
8,1 1,12
8,11 ,12,13
8,11 ,12,13
8,1 1,12
8,11 ,12,13
10,1 1,12,13
0
VD DIO
VSSA
VDDA
0
TD _A0
TD _A1
TD _A2
TD _B0
TD _B1
TD _B2
DSTo
TD_A3T
TD_B3T
R D_A3F
R D_B3F
2
3V3
4
GPCL K0
GPCL K1
T_ SYNC
T_CLK
F0
3
1 0k
1 0k
R 90
TP34
TP37
TP38
3V3
R 89
22 .1
TP46
TP45
3V3
D13
B14
C13
A13
C11
A12
B10
B9
C9
A7
D7
A6
B5
D6
B4
D5
U15
R13
U14
T12
R11
T11
U10
U9
U8
T7
P7
T6
U4
P6
U3
R4
D15
E14
C17
E15
F14
E17
F16
F17
P17
N15
K15
L17
L15
K17
H16
M16
J17
H17
U 16A
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
GPCLK0
GPCLK1
GPCLK2
GPCLK3
GPCLK4
GPCLK5
GPCLK6
GPCLK7
PDC
PFS
NTWK2
NTWK1
H110-MODE
M-MODE
MODE16
RESET
XTALIN
XTALOUT
R301
(CS4)
GA3
GA2
GA1
GA0
22 .1
R 59
Demux Mode
I RQ2sb
BAs[31 :27]
BDs[7:0]
CLKFRM
8,1 1,13
IRQ3sb
6 FRM_ RSTb
5,8
GPL2s
8
GPL3s
F ALCCSb
8, 11
BDs[7:0]
BAs[31 :24]
TD_ B3F
TD_ A3F
T_ CLK
C LK3F
RD _A3F
T_ SYNC
RD _B3F
SYNC3F
NTWK_C LK
(CS3)
5 RN 24D 4
6 RN 24C 3
22.1
R100
8 R N24A 1
7 R N24B 2
22.
TP35
TP36
R103
R102
6,8,1 2,13 GA[0: 3]
22.1
8,1 1,13 I RQ2sb
8, 11 TSI CSb
8
GPL0s
8
GPL1s
CLKFRM
HRESE Tsb
NTWK_C LK
R101
10
0.1 uF
C 145
10
R 96
GND
OUT
VCC
4
3V3
10,1 1,12
12
12
10,1 1,12 DSTi
TD_A 3Fs
TD_B 3Fs
RD_ A3T
RD_ B3T
8,11 ,12 R D_A0
8,11 ,12 R D_A1
8,11, 12,13 R D_A2
EN
U 15
G17
G16
R 78 (*)
R77
(*)
5VExt
MI302 5HAH-16.384MHz
0.1uF
C 140
8,11, 12,13 R D_B0
8,11 ,12 R D_B1
EXTMST 8,11, 12,13 R D_B2
TD_A3T
TD_ A3F
TD_B3T
TD_ B3F
RD_ A3T
RD _A3F
RD_ B3T
RD _B3F
T_ CLK
C LK3F
T_ SYNC
SYNC3F
TD_A 3Fs
TD_B 3Fs
C118
FRMt oTSI 6
C160
0.1uF
0.1uF
C116
C159
J P5
C 117
+ C 17
TSI
PEF2 4471
Par t1
22 .1
BAs 31
BAs 30
BAs 29
BAs 28
BAs 27
BAs 26
BAs 25
BAs 24
BD s7
BD s6
BD s5
BD s4
BD s3
BD s2
BD s1
BD s0
IRQ3sb
TP2
TP1
T_ CLK1
3V3
3
HSGA0
HSGA1
HSGA2
HSGA3
U3
75
66
67
68
69
70
65
56
60
61
62
63
64
43
44
45
46
47
48
49
50
40
39
38
37
36
33
32
31
57
13
52
53
54
78
79
73
76
77
CT_D0
CT_D1
CT_D2
CT_D3
CT_D4
CT_D5
CT_D6
CT_D7
CT_D8
CT_D9
CT_D10
CT_D11
CT_D12
CT_D13
CT_D14
CT_D15
CT_D16
CT_D17
CT_D18
CT_D19
CT_D20
CT_D21
CT_D22
CT_D23
CT_D24
CT_D25
CT_D26
CT_D27
CT_D28
CT_D29
CT_D30
CT_D31
CT_FRAME_A
CT_FRAME_B
FR_COMP
CT_NETREF1
CT_NETREF2
CT_C8_A
CT_C8_B
CT_EN
CT_RESET
SCLKx2
SCLK
C4
C2
C16C16+
TDO
TRST
TMS
TCLK
TDI
RCLK
RDO
RPA/SYPR
RPB/RSIG
RPC/RSFP/RFM
RPD/RMFB
SCLKR
XDI
XPA/SYPX
XPB/XSIG
XPC/TCLK/XCLK
XPD/TFS
SCLKX
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
INT
RESET
RD
WR
CS
3V3
SEC/FSC
SYNC
MCLK
CLK1
CLK2
R 81
(*)
(*) R 82
TDOTSI
7
22 .1
TP44
TP39
TP43
0
0
TMS
TC LK
SCLKx2
S CLK
R 99
CT_E Nb
HRESET sb
FRAM EA
FRAM EB
FR_COMP
NETRE F1
NETRE F2
CT 8A
CT 8B
CTD0
CTD1
CTD2
CTD3
CTD4
CTD5
CTD6
CTD7
CTD8
CTD9
CTD 10
CTD 11
CTD 12
CTD 13
CTD 14
CTD 15
CTD 16
CTD 17
CTD 18
CTD 19
CTD 20
CTD 21
CTD 22
CTD 23
CTD 24
CTD 25
CTD 26
CTD 27
CTD 28
CTD 29
CTD 30
CTD 31
HSGA[0 :3] 12 ,13
A15
D12
A14
B12
D11
B11
A10
A9
A8
B7
C7
B6
A4
C5
A3
C4
T14
P12
T13
U12
P11
U11
R9
T9
T8
U6
R7
U5
R5
T4
P5
T3
D16
G15
K2
M14
H15
F15
G14
R1
K16
N2
L3
F3
D2
H1
F1
N14
P16
P15
R16
R17
TDO FRM
FR1
CTD0
CTD1
CTD2
CTD3
CTD4
CTD5
CTD6
CTD7
CTD8
CTD9
CTD 10
CTD 11
CTD 12
CTD 13
CTD 14
CTD 15
4
3
2
1
1
2
3
4
4
3
2
1
2
1
3
4
1
2
3
4
4
3
2
1
CTD 20
CTD 21
CTD 22
CTD 23
2
3
4
1
CTD 16
CTD 17
CTD 18
CTD 19
CTD 24
CTD 25
CTD 26
CTD 27
1
4
3
2
R5
1 0k
FR2
R N4
RN 28
R N3
RN 25
R N2
RN 22
R N1
RN 20
3
2
7
5
14
15
16
17
18
5
6
7
8
24.
HTD4
HTD5
HTD6
HTD7
HTD0
HTD1
HTD2
HTD3
2
8
7
6
5
24.
HTD 20
HTD 21
HTD 22
HTD 23
HTD 16
HTD 17
HTD 18
HTD 19
HTD8
HTD9
HTD 10
HTD 11
5
6
7
8
24.
5
6
7
8
24.
8
7
6
5
24.
HTD 24
HTD 25
HTD 26
HTD 27
HTD 12
HTD 13
HTD 14
HTD 15
7
6
5
8
24.
HTD 28
HTD 29
HTD 30
HTD 31
7
8
6
5
24.
8
5
6
7
24.
NETRE F1
R 84
22.1
CT 8A
FRAM EB
FRAM EA
R 95
R 87
R 88
R 94
0
0
0
0
0
NETRE F2
22.1
CT 8B
R 85
0
2 0k
20k
R 93
R 75
FR_COMP
R2
0
R 76
SCLKx2
R 86
C 11
(*)
S CLK
C 12
(*)
2.7
2.7
100
R 57
R 28
(*)
0
TMS
TC LK
R 29
(*)
8
7
6
1
2
3
0
CTD0
CTD1
CTD2
CTD3
CTD4
CTD5
CTD6
CTD7
CTD8
CTD9
CTD 10
CTD 11
CTD 12
CTD 13
CTD 14
CTD 15
CTD 16
CTD 17
CTD 18
CTD 19
CTD 20
CTD 21
CTD 22
CTD 23
1
2
3
4
9
8
7
6
1
2
3
4
8
9
7
6
1
2
3
4
9
8
7
6
3
2
1
4
9
6
7
8
18K.
RN 29
0.7V
18K.
RN 26
18K.
RN 23
18K.
RN 21
12
12
HTD[0 :31]
12
HTNET REF_1
HTNET REF_2
HT_F RAME_A 12
12
12
HT_F RAME_B 12
HT_ C8_A 12
HFR_COMP
HT_ C8_B 12
H SCLK_D
H SCLK 12
R 58
R 62
R 69
R 66
5.6
5.6
5.6
5.6
1
7
CT_RE F2
3V3
+
-
U 13
+IN2
-IN2
- -IN1
+ +IN1
MC 33202
OUT1
OUT2
CT_RE F1
2
3
1
3V3
R 74
20k
R 73
5.6k
C106
0.1uF
6,7
5
6
TMS
TDO ISP 6
TMS
TDO ISP
CT_ ENb 12
6,8,10, 11,12,13
HRESE Tsb
6,7
R302
(*)
TCLK
HRESET sb
0
TCLK
HRESE Tsb
CT_ ENb
VS SA
P6
1
2
3
4
5
6
7
8
1
E1/T1
RJ45 SHLD
Sh eet
TDM Periherals
t 13, 2002
9
of
CT_EN input is grounded to provide
H.110 bus enable b y default
C 13
(*)
Tuesday, Augus
Document Nu mber
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
Date:
Size
C
MSC8102ADS
Motorola Se miconductor Israel Ltd.
C 14
(*)
Hot Swap is not s upported
TDO FRM
TDO ISP
14
15
16
11
10
9
10 K.
5
10
R N19
CTD 24
CTD 25
CTD 26
CTD 27
CTD 28
CTD 29
CTD 30
CTD 31
M+
U6
RECEIVE
1:1
P+
S+
S+
M
M+
P-
P+
S-
M
PSTRANSMIT
1:2.4
T1144
Only one of two resis tors from
pairs *R81,*R82 and *R28,*R29
may be placed to change
JTAG chain confi guration
R 64
R 65
n C4 10,1 1,12
CTD 28
CTD 29
CTD 30
CTD 31
R3
1 0k
3V3
C 77
VS SA
XDOP
RDIN
RDIP
0.1uF 0.1 uF
C 78
R4
10k
E1/T1 Framer
PEB 2256
XDON
TRST
TDI
TMS
TCK
TDO
2
8
VCC
VEE
5
10
5
10
5
10
5
10
15
PIL OT
R ev
D
C
B
A
123
MSC8102ADSUM/D Ver. 1.2
User’s Manual
8,11 ,12,13 TD_B3
8,11 ,12,13 R D_B3
8,11, 12,13 TDM CLK3
12
C 27
C139
2
3
4
1
6
7
8
9
1
15
TSI
PEF24 471
Power
C130
C 138 C 131
C 72
10pF -2KV
A/B
G
IDT74 CBTLV3257PG
C147
C156
C 73
VS SA
RJ45 43 202-8919
TD_ B3F
3V3
C 133 C 148
C144
C 68
VS SA
11
12
*R78 assembled as default.
*R77 is assembled in pl ace of *R78
depending H.110 voltage environment
U 16B
C149
C135
C69
8-bi t Non-Multiplex
Intel Bus Mode
10pF -2KV
8,11, 12,13 TDMSYN3
J16
J15
RSV
RSV
C134
C 129 C 157
C 63
0.1uF 0.1 uF 0.1 uF 0.1uF 0.1uF 0.1uF
C 64
3
9
10
G2
H3
G1
H2
J3
K1
K3
L1
D0
D1
D2
D3
D4
D5
D6
D7
BD s7
BD s6
BD s5
BD s4
BD s3
BD s2
BD s1
BD s0
4
10pF -2KV
C
B
A
C158
0.1uF 0.1uF 0.1 uF 0.1 uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1 uF 0.1uF
C132
10uF
4
10pF -2KV
6
VDDX
4
VDDR
L2
L4
N1
M3
P1
M4
N3
P2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
E3
D1
E2
G3
G4
A0
A1
A2
A3
A4
BAs 31
BAs 30
BAs 29
BAs 28
BAs 27
ALE
IREQ
CS
RD/DS
WR/R/W
F4
L14
N17
E4
C1
2
1
0.1uF 0.1uF 0.1 uF 0.1 uF 0.1uF 0.1uF 0.1uF 0.1 uF 0.1 uF 0.1uF
5
VSSX
8
VSSR
1
NC4
NC3
NC2
NC1
80
74
20
19
9
24
34
41
58
71
VDD
VDD
VDD
VDD
VDD
VDD
21
22
23
26
27
28
29
30
VSS
VSS
VSS
VSS
VSS
VSS
B8
B13
R12
U7
VDDIO
VDDIO
VDDIO
VDDIO
D15
D14
D13
D12
D11
D10
D9
D8
72
59
42
35
25
10
1
2
ALE
BLE
IM
DBW
51
55
11
12
C2
E1
J2
M1
N4
R6
R10
R14
M15
D17
B15
C10
A5
D8
D10
H4
H14
K4
P8
P10
K14
L16
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D3
F2
J1
M2
P3
T5
R8
T10
U13
P13
N16
M17
E16
C14
C12
A11
C8
C6
B2
B16
C3
C15
D4
D9
D14
H8
H9
H10
J4
J8
J9
J10
J14
K8
K9
K10
P4
P9
P14
R3
R15
T2
T16
Figure 5-14 Schematics. Page 9
Support Info
P1
5
AGND1
C3
10uF
R 20
1 0k
C 71
R 35
10k
3V 3A
AGND1
0.1uF
3V 3A
U1
4
R 14
-IN1 OUT1
+IN1 +
MC3 3202
10k
3V 3A
+IN2 +
-IN2 OUT2
2
3
AGND1
R 25
3V 3A
-IN1 OUT1
+IN1 +
MC3 3202
10k
5
6
U2
2
3
+IN2 +
-IN2 -
+
4.7k
R 21
AGND1
OUT2
5
6
C 70
0.1uF
1
7
R 13
1 0k
1%
1
7
R 24
1 0k
1%
10uF
+ C4
4.7k
R 12
R 19
1 0k
1%
R 34
1 0k
1%
3V 3A
R 98
1 0k
3V3
C142
0.1 uF
C137
0.1 uF
UAR TTX
3V3
NORM
3.3V clean
J P1
2
1
L1
2
3V 3A
C 65
3
3V3
MT923 03/PR/GP1N
0.1uF
RXDU ART
TXDUART
C 79
AUX
RESET
SCLK
CS
DATA1
DATA2
MCLK
C4i
F0i
DSTi
DSTo
MIC1-
MIC1+
MIC0-
MICB0
MIC0+
C 66
23
26
25
5
4
3
2
1
10
11
9
8
30
12
0.1uF
C143
0.1uF
C136
0.1uF
C141
2.2nF
C 84
21
22
0.01 uF
AGND1
4
5
6
7
8
9
10
11
3
27
26
DS To
1 uF
2.2nF
C 74
2.2nF
C 75
U 14
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
T3OUT
V-
V+
VCC
75k
R 46
BEAD FERR ITE
130
130
AGND1
SHDN
C1+
C1C2+
C2T1IN
T2IN
T3IN
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
EN
DGND
MAX3241ECAI
R1OUTB
R2OUTB
RS-232
HRESE Tsb
8, 12 CC LK
6,15 CO DEC_ENb
6,8 ,12 CDATA
9,1 1,12 n C4
9,1 1,12 F0
9,1 1,12 DSTi
9,11, 12,13 DS To
R 32
130
R 33
R 30
130
R 31
1
3
8,1 1,12 TIMER3
22
28
24
1
2
14
13
12
21
20
19
18
17
16
15
25
23
3
U4
P10
SPK+
SPK-
EAR1+
EAR1-
MICB2
MICD2
MIC2+
MIC2EAR2+
EAR2-
MICB3
MIC3+
MIC3EAR3+
EAR3MICD3
RS232-2
3-pi n Header
42
43
33
32
17
18
19
20
36
35
13
15
16
39
38
14
C6
10uF
C7
10uF
2
P5
SPEAKER
LEFT
RIGHT
LINE OUT
3
11
10
2
1
AGND1
2
10uF
+ C 10
0.1uF
C 87
0.1uF
C 80
0.1 uF
C 86
0.1uF
C 85
0.1uF
C 81
Motorola Se miconductor Israel Ltd.
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
Document Nu mber
1
1
Sh eet
CODEC,UART
MSC8102ADS
Tuesday, Augus
t 13, 2002
Date:
Size
C
10
of
15
PIL OT
R ev
D
C
B
A
Figure 5-15 Schematics. Page 10
+
3
11
10
2
1
LINE IN
LEFT
RIGHT
HEADPH/MIC
C5
10uF
C 67
0.1uF
AGND1
R 22
1 0k
AGND1
AGND1
6,8,11 ,12,13 UART TX
6,8, 11,12 UA RTRX
6, 15 RS232EN _2b
4
1
2
+
+
6
29
44
34
40
VDDD
VDDA
VDDP0
VDDP12
VDDP3
8
VCC
VEE
4
8
VCC
VEE
4
D
C
B
A
5
MSC8102ADSUM/D Ver. 1.2
User’s Manual
124
VREF
24
GNDA
SUB
GNDD
GNDP0
GNDP1
GNDP23
28
27
7
41
31
37
1
2
3
1
2
Support Info
D
C
B
A
5
(CS4)
Ah0
Ah1
Ah2
Ah3
Ah4
Ah5
Ah6
Ah7
Ah8
Ah9
Ah 10
Ah 11
Ah 12
Ah 13
Ah 14
Ah 15
A s0
A s1
A s2
A s3
A s4
A s5
A s6
A s7
A s8
A s9
As10
As11
As12
As13
As14
As15
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
ADDR -H
ODD
P21
EVEN
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ODD
ODD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Ah 16
Ah 17
Ah 18
Ah 19
Ah 20
Ah 21
Ah 22
Ah 23
Ah 24
Ah 25
Ah 26
Ah 27
Ah 28
Ah 29
Ah 30
Ah 31
(BM0)
(BM1)
(BM2)
As16
As17
As18
As19
As20
As21
As22
As23
As24
As25
As26
As27
As28
As29
As30
As31
3, 13 TShb
3,4 ,13 PSDVA Lhb
3,4 BCT L0hb
3,4 CAShb
3,4, 5,8 RAShb
3
TTh1
3,4 ,5 W Ehb
3,4 ,5 SDA10h
3,4, 5,8 DQM h0
3,4, 5,8 DQM h1
3,4, 5,8 DQM h2
3,4, 5,8 DQM h3
3,4, 5,8 DQM h4
3,4, 5,8 DQM h5
3,4, 5,8 DQM h6
3,4, 5,8 DQM h7
3,8 ,13 UPM WAIThb
ADDR -S
EVEN
.
.
.
.
.
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EVEN
P3
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
SYS1 -S
LA- MICTOR38
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
P7
LA- MICTOR38
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
1
3
5
7
9
TP12
11
TP11
13
15
17
19
21
23
25
27
29
31
(NMI_OUTsb) 33
35
37
(CS3)
TSsb
PSDVAL sb
TTs0
TTs1
TTs2
TTs3
TTs4
TAsb
TEAsb
AR TRYsb
AACKsb
TBSTsb
IRQ5hb
NMI sb
PRS Tsb
LA- MICTOR38
TP8
TP7
TP6
TP5
(HR/Wb)
(HTAb)
(HDBS0b)
(HDBS1b)
(HDBS2b)
(HDBS3b)
(HDBS4b)
(HDBS5b)
(HDBS6b)
(HDBS7b)
4
EVEN
ODD
P16
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
8
LA-M ICTOR38
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
60x, M isc
CL KM1 3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
CLKS1
CLKS2 8
BNKSELs0 6,8
B NK1
8
B NK0
8
EE0s
8,1 2,13
EE1s
8,1 2,13
I RQ1sb 5,8 ,13
ABBsb 8, 13
D BBsb 8,1 3,15
TDOs 6,8
TDIs 6,8
SRESE Tsb 6,8 ,13
HRESET sb 6,8,9,1 0,12,13
4
5,6
F CShb
Ds[0:31]
FC Ssb
(CS0)
(CS4)
D h0
D h1
D h2
D h3
D h4
D h5
D h6
D h7
D h8
D h9
Dh10
Dh11
Dh12
Dh13
Dh14
Dh15
Ds0
Ds1
Ds2
Ds3
Ds4
Ds5
Ds6
Ds7
Ds8
Ds9
D s10
D s11
D s12
D s13
D s14
D s15
(HDBS4b)
(HDBS5b)
(HDBS6b)
(HDBS7b)
(GPL3)
(GPL2)
(GPL1)
(GPL0)
(WE0)
(CS0)
CL KM2 3
MODC Kh1 3,6
BNKSE Lh1 3,6
BNKSE Lh2 3,6
IRQ1hb 3,8 ,13
IRQ2hb 3,1 2,13
IRQ3 hb 3,1 2,13
IRQ4hb 3,1 2,13
IRQ7 hb 3,5 ,13
TAhb 3,13
TEAhb 3, 13
H BCSb 3,4, 6,8
ATMCSb 3,6 ,7
CS6hb 3,4
PR STb 3,5, 6,15
SRE SEThb 3,6 ,13
HRES EThb 3,6, 12,13
3,4, 5,8 Dh[0:3 1]
2
4
6
8 (BNKSELh0)
10 (MODCKh2)
12 (MODCKh3)
14
16
18
20
22
24
26
28 (CS3)
30 (CS5)
32 (CS6)
34
36
38
5,8
4,5 ,8
5,8 C ASsb
5,8 R ASsb
5,8 WE sb
5,8 SDA10s
5,8 DQM s0
5,8 DQM s1
5,8 DQM s2
5,8 DQM s3
8 DQM s4
8 DQM s5
8 DQM s6
8 DQM s7
4,8 BCT L0sb
4,8 BCT L1sb
8,9 F ALCCSb
6,8, 13 TC Ks
6,8 TMSs
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
DATA H-H
ODD
P18
EVEN
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
ATMTS OC
LA- MICTOR38
7
7 ATMTXD[0 :7]
ODD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
7 ATMRXD[0:7]
DATA H-S
EVEN
P11
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LA- MICTOR38
ODD
SYS2 -S
EVEN
P9
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LA- MICTOR38
3
Dh16
Dh17
Dh18
Dh19
Dh20
Dh21
Dh22
Dh23
Dh24
Dh25
Dh26
Dh27
Dh28
Dh29
Dh30
Dh31
D s16
D s17
D s18
D s19
D s20
D s21
D s22
D s23
D s24
D s25
D s26
D s27
D s28
D s29
D s30
D s31
CLK M3
H D0
H D1
H D2
H D3
H D4
H D5
3
(CS2)
(BADDR29)
(BADDR30)
(BADDR31)
BC SRCSb 3,6
(CS1)
ATMTXD0
ATMTXD1
ATMTXD2
ATMTXD3
ATMTXD4
ATMTXD5
ATMTXD6
ATMTXD7
ATMRX D7
ATMRX D6
ATMRX D5
ATMRX D4
ATMRX D3
ATMRX D2
ATMRX D1
ATMRX D0
5,8
H D[5:0]
SDRMCSsb
(SWTE)
(DSISYNC)
(DSI64)
(MODCK1)
(MODCK2)
(CNFGS)
TSI Zs3 8
TSI Zs2 8
TSI Zs1 8
TSI Zs0 8
B ADDR28s 8
B ADDR27s 8
IRQ5sb 8, 13
IRQ2sb 8,9 ,13
I RQ3sb 8,9 ,13
RSTCFGs 6,8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
8
3,5 SDRMCS hb
(CS2)
ODD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
EXC LKs
3,4, 5,8 Dh[31: 63]
EVEN
P22
UTOPI A-8
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LA-M ICTOR38
8
TD MCLK0
TD _A0
TD _B0
RD _A0
RD _B0
TD MCLK1
TD _A1
TD _B1
RD _A1
RD _B1
TDMSYN1
TD MCLK2
TD _A2
TD _B2
RD _A2
RD _B2
TDMSYN2
4,5 ,8 Ds[31:6 3]
8,9 ,12
8,9, 12,13
8,9, 12,13
8,9 ,12
8,9, 12,13
8,9 ,12
8,9 ,12
8,9 ,12
8,9 ,12
8,9 ,12
8,9 ,12
8,9, 12,13
8,9, 12,13
8,9, 12,13
8,9, 12,13
8,9, 12,13
8,9, 12,13
2
2
Dh32
Dh33
Dh34
Dh35
Dh36
Dh37
Dh38
Dh39
Dh40
Dh41
Dh42
Dh43
Dh44
Dh45
Dh46
Dh47
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
ATM RSOC 7
AT MRCLK 7
AT MRCA 7
ATMRXE Nb 7
AT MFCLK 7
ATMTC Ab 7
ATM TXENb 7
ATMTC LK 7
ATMRXPRTY 7
ATMTXP RTY 7
EE 0h 3,6 ,13
EE 1h 3,6 ,13
SCC1R TSb 7
SC C1TXD 7
SCC1R XD 7
SCC1C TSb 7
SC C1DSRb 7
D s32
D s33
D s34
D s35
D s36
D s37
D s38
D s39
D s40
D s41
D s42
D s43
D s44
D s45
D s46
D s47
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
DATA L-H
EVEN
ODD
P19
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LA- MICTOR38
DATA L-S
EVEN
ODD
P12
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
.
.
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LA- MICTOR38
PRPH -S
EVEN
P4
SCL
SDA
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ODD
.
.
.
.
.
VDC
GND
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LA- MICTOR38
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Dh48
Dh49
Dh50
Dh51
Dh52
Dh53
Dh54
Dh55
Dh56
Dh57
Dh58
Dh59
Dh60
Dh61
Dh62
Dh63
D s48
D s49
D s50
D s51
D s52
D s53
D s54
D s55
D s56
D s57
D s58
D s59
D s60
D s61
D s62
D s63
CS0hb
3,6
C S1sb 8
TDMSYN0
TD MCLK3
TD _A3
TD _B3
R D_A3
R D_B3
TDMSYN3
F0
n C4
DS To
DSTi
UAR TTX
UA RTRX
TIMER0
TIMER1
TIME R_CLK2
TIMER3
1
8,9 ,12
8,9, 12,13
8,9, 12,13
8,9, 12,13
8,9, 12,13
8,9, 12,13
8,9, 12,13
9,1 0,12
9,1 0,12
9,10, 12,13
9,1 0,12
6,8,1 0,12,13
6,8, 10,12
8,12
8,12
8, 12
8,10 ,12
Motorola Se miconductor Israel Ltd.
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
1
Host Side
11
of
15
Slave Side
Sh eet
LA MICTOR Connectors
MSC8102ADS
Tuesday, Augus
Document Nu mber
t 13, 2002
Date:
Size
C
PIL OT
R ev
D
C
B
A
125
MSC8102ADSUM/D Ver. 1.2
User’s Manual
3,4, 6,8 HC Sb
3,4, 5,8 Ah[0 :31]
As[0:3 1]
8 ,9 TSI CSb
4,5 ,8
8
8
8
8
8
8
8
8,13
8,13
8
8
8
3,8 ,13
6,8,1 2,13
5,6,8, 12,15
5
Figure 5-16 Schematics. Page 11
Support Info
D
C
4,8
4
4
XB S[0:7]
XA [7:29]
XD [0:63]
6,8, 9,13 GA[0: 3]
HTD[0 :31]
9, 13 HSGA[0: 3]
9
5
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XD8
XD9
XD10
XD11
XD12
XD13
XD14
XD15
XD16
XD17
XD18
XD19
XD20
XD21
XD22
XD23
XD24
XD25
XD26
XD27
XD28
XD29
XD30
XD31
XBS0
XBS1
XBS2
XBS3
XBS4
XBS5
XBS6
XBS7
XA7
XA8
XA9
XA10
XA11
XA12
XA13
XA14
XA15
XA16
XA17
XA18
XA19
XA20
XA21
XA22
XA23
XA24
XA25
XA26
XA27
XA28
XA29
XD32
XD33
XD34
XD35
XD36
XD37
XD38
XD39
XD40
XD41
XD42
XD43
XD44
XD45
XD46
XD47
XD48
XD49
XD50
XD51
XD52
XD53
XD54
XD55
XD56
XD57
XD58
XD59
XD60
XD61
XD62
XD63
GA0
GA1
GA2
GA3
H SGA0
H SGA1
H SGA2
H SGA3
HTD0
HTD1
HTD2
HTD3
HTD4
HTD5
HTD6
HTD7
HTD8
HTD9
HTD 10
HTD 11
HTD 12
HTD 13
HTD 14
HTD 15
HTD 16
HTD 17
HTD 18
HTD 19
HTD 20
HTD 21
HTD 22
HTD 23
HTD 24
HTD 25
HTD 26
HTD 27
HTD 28
HTD 29
HTD 30
HTD 31
HRESE Tsb
7
4
XTCK
HTD0
HTD4
HTD8
HTD 11
HTD 13
HTD 16
HTD 19
HTD 21
HTD 24
HTD 27
HTD 29
XBS5
XD63
XD59
XD56
XD52
XD49
XD45
XD42
XD38
XD35
XA21
XA24
XA25
XA29
XD1
XD7
XD12
XA12
XH BCSb
4
XCS6b
XA18
3,1 1,13 IRQ2hb
XD30
XD26
XBS3
XD21
XD18
4
L4T XD
9,10 ,11,13 DSTo
L4 RXD
L3T XD
L3 RXD
L2T XD
L2 RXD
L1TXD
L1 RXD
TD_A3
R D_A3
TD_A2
R D_A2
TD_A1
R D_A1
TD_A0
8,9 ,11 R D_A0
6,8
TES Ts
8, 11 TIMER0
7
7
7
7
7
7
7
8,9, 11,13
8,9, 11,13
8,9, 11,13
8,9, 11,13
8,9 ,11
8,9 ,11
8,9, 11,13
4
3V3E xt
IRQ2hb
3V3
4
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
J 1A
5V
TCK
INTA#
IPMB PWR
BRSVP1A5
REQ#
AD30
AD26
C/BE3#
AD21
AD18
3.3V
DEVSEL#
3.3V
SERR
3.3V
AD12
3.3V
AD7
3.3V
AD1
5V
J 2A
CLK1
CLK2
CLK4
3.3V
C/BE5#
AD63
AD59
AD56
AD52
AD49
AD45
AD42
AD38
AD35
BRSVP2A15
BRSVP2A16
BRSVP2A17
BRSVP2A18
GND
CLK5
CLK6
GA4
J 4A
CT_D0
CT_D4
CT_D8
CT_D11
CT_D13
CT_D16
CT_D19
CT_D21
CT_D24
CT_D27
CT_D29
4
XA17
XD29
XD17
XHC Sb
XA23
L2C LK
L4CLK
TIMER1
G A3
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
J 1B
3
3,6 ,13 TRSThb
4
XTMS
XD33
XD40
XD47
XD54
XD61
XBS7
3V3E xt
3V3E xt
HSGA2
R 72
2 .4k
3V3
GA2
HRES EThb
IRQ3 hb
SY SENb
HRESE Tsb
XA7
XD3
XD8
XD14
XA13
XGPL2
XD16
XD23
XD28
5,6,8 ,11,15 PRS Tsb
4
3,1 1,13
IRQ3 hb
4, 13 SYS ENb
HRESE Tsb
8,9, 11,13 TD_B2
8,9 ,11 TD_B1
8,9,1 1,13 TD_B0
8, 10
CC LK
8, 11 TIM ER_CLK2
TDM0RCLK
TDM1RCLK
TDM2RCLK
TDM3RCLK
HRES EThb
3,6, 11,13 XA27
4 XGPL0
4 XGPL1
4 XGPL3
GA2
HTD1
HTD6
HTD 10
HTD 12
HTD 15
HTD 18
HTD 20
HTD 23
HTD 26
HTD 28
HTD 31
HSGA2
9 CT_ ENb
L3C LK
DSTi
7
L1C LK
9 GPCLK0
9 GPCLK1
7
9,10 ,11
-12V
5V
INTB#
HEALTHY#
BRSVP1B5
GND
AD29
GND
IDSEL
GND
AD17
FRAME#
GND
IPMB SCL
GND
AD15
GND
AD9
GND
AD4
5V
REQ64#
J5B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
8,9, 11,13 TD_B3
IN/C
NP
NP
IN/C
NP
NP
PFS1#
RSVD
/CT_Reset
GA3
SGA3
+3.3V
CT_D5
CT_D9
+5V
CT_D14
CT_D17
+5V
CT_D22
CT_D25
+3.3V
CT_D30
J 4B
GND
CLK3
GND
BRSVP2B4
GND
AD62
GND
AD55
GND
AD48
GND
AD41
GND
AD34
GND
BRSVP2B16
GND
BRSVP2B18
GND
GND
GND
GA3
J 2B
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B15
B16
B17
TP21 B18
B19
B20
B21
B22
B23
B24
B25
1
3V3E xt 5VExt
J P6
2
CT RST
HSGA3
XA14
XD15
XD9
XA9
XD4
XA20
XD62
XD55
XD48
XD41
XD34
GA3
XA28
HTD5
HTD9
HTD 14
HTD 17
HTD 22
HTD 25
HTD 30
7
H SGA3
HRESE Tsb
7
8, 11
8,1 0,11 TIMER3
8,9 ,11 TD MCLK0
8,9 ,11 TD MCLK1
8,9, 11,13 TD MCLK2
8,9, 11,13 TD MCLK3
-Vbat
NP
NP
VRG
NP
NP
-SEL Vbat
PFS0#
+12V
GA4
SGA4
J 5A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
3
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
J1C
TRST#
TMS
INTC#
3.3V
RST#
3.3V
AD28
3.3V
AD23
3.3V
AD16
IRDY#
3.3V
IPMB SDA
3.3V
AD14
3.3V
AD8
3.3V
AD3
3.3V
ENUM#
J2C
REQ1#
SYSEN#
GNT3#
C/BE7#
3.3V
AD61
3.3V
AD54
3.3V
AD47
3.3V
AD40
3.3V
AD33
FAL#
DEG#
PRST#
BRSVP2C18
RSV
RSV
RSV
GA2
J4C
CT_D1
CT_D6
CT_D10
CT_D12
CT_D15
CT_D18
CT_D20
CT_D23
CT_D26
CT_D28
CT_D31
6
CLKX
TDOi
GP L4
4
3
3V3E xt
XA19
XD25
XD20
XA15
XD11
XD6
XD0
HRS T2b
HRS T3b
TP63
UPMWAIThb
XBS4
XD58
XD51
XD44
G A1
3V3E xt 5VExt
TDM0TSYN
TDM1TSYN
TDM2TSYN
TDM3TSYN
H SGA1
TP20
GA1
XD37
XP SDVALb
6,13 HRS T2b
6,13 HRS T3b
4
HT D2
HT D7
H SGA1
9,1 0,11 F0
L1SY NC
7 L3SY NC
7
6,8 ,10 CDATA
8,1 1,13 E E0s
6,8, 10,11 UA RTRX
8,9 ,11 TDMSYN0
8,9 ,11 TDMSYN1
8,9, 11,13 TDMSYN2
8,9, 11,13 TDMSYN3
IN/C
NP
NP
IN/C
NP
NP
RSVD
RSVD
/CT_EN
GA2
SGA2
J5C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
2
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
J1D
+12V
TDO
5V
INTP
GND
CLK
GND
AD25
GND
AD20
GND
BD_SEL#
STOP#
GND
PAR
GND
AD11
M66EN#
AD6
5V
AD0
3.3V
J2D
GNT1#
GNT2#
REQ4#
GND
C/BE4#
GND
AD58
GND
AD51
GND
AD44
GND
AD37
GND
REQ5#
GND
REQ6#
GND
RSV
GND
RSV
GA1
6
HRST 1b
TD Io
IRQ4 hb
6, 13
3,1 1,13
GA0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
J 1E
5V
TDI
INTD#
INTS
GNT#
AD31
AD27
AD24
AD22
AD19
C/BE2#
TRDY#
LOCK#
PERR#
C/BE1#
AD13
AD10
C/BE0#
AD5
AD2
ACK64#
5V
J 2E
REQ2#
REQ3#
GNT4#
C/BE6#
PAR64
AD60
AD57
AD53
AD50
AD46
AD43
AD39
AD36
AD32
GNT5#
BRSVP2E16
GNT6#
BRSVP2E18
RSV
RSV
RSV
GA0
J 4E
CT_D3
GND
SCLK_D
SCLK
CT_NETREF_2
CT_NETREF_1
CT_C8_B
CT_C8_A
/FR_COMP
/CT_FRAME_B
/CT_FRAME_A
VBatRtn
NP
NP
VRGRtn
NP
NP
SELVbatRtn
RSVD
CT_MC
GA0
SGA0
J 5E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Motorola Se miconductor Israel Ltd.
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
IRQ4 hb E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
TP65
TP64
HRST 1b
XD31
XD27
XD24
XD22
XD19
XBS2
XA11
XA10
XBS1
XD13
XD10
XBS0
XD5
XD2
XA8
TDM0RSYN
TDM1RSYN
TDM2RSYN
TDM3RSYN
3V3
H SGA0
TP19
TP18
G A0
XA26
XA22
XBS6
XA16
XD60
XD57
XD53
XD50
XD46
XD43
XD39
XD36
XD32
H SCLK_D
HS CLK
HTNETR EF_2
HTNETR EF_1
HT_C 8_B
HT_C 8_A
HFR_COMP
HT_FR AME_B
HT_FR AME_A
HT D3
4,6 BXBCT L0
4,7 BAh 31
4,5 ,7 BAh 30
9
9
9
9
9
9
9
9
9
H SGA0
9,10 ,11
n C4
6,8, 11,13 NMI sb
7 L4SY NC
CLK2
7 L2SY NC
7
8,9 ,11 RD _B1
8,9, 11,13 RD _B2
8,9, 11,13 RD _B3
J4D
CT_D2
CT_D7
GND
+3.3V
+3.3V
GND
GND
+5V
GND
+5V
3.3V
IN/C
NP
NP
IN/C
NP
NP
RSVD
RSVD
-12V
GA1
SGA1
J5D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
8,9, 11,13 RD _B0
8,1 1,13
EE1s
UART TX
6,8,1 0,11,13
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Tit le
1
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
MSC8102ADS
Tuesday, Augus
Document Nu mber
t 13, 2002
1
J 1F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J 2F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J4F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NP
NP
NP
NP
NP
NP
FG
FG
FG
FG
FG
J5F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Sh eet
12
cPCI Expansion Connectors
Date:
Size
C
of
15
PIL OT
R ev
D
C
B
A
MSC8102ADSUM/D Ver. 1.2
User’s Manual
126
B
A
6,8,9, 10,11,13 HRESE Tsb
5
Figure 5-17 Schematics. Page 12
Support Info
D
C
B
A
1k
1k
5
R118
1k
R113
1k
1k
HRESEThb
R112
SRESEThb
R152
1k
SRESETsb
R67
R109
TEAhb
HRES ETsb
TEAsb
10k
10k
5.1k
10k
R56
R120
UARTTX
R23
10k
DBUFX ENb
R106
10k
DB UFBENb
R121
ABBsb
10k
UPMWAIT hb R155
PSDVALhb
R300
R N7
9
8
7
6
4
3
2
1
AACK sb
EE1s
DSTo
TRSTsb
TRSThb
9
8
7
6
4
3
2
1
R141
6
6
6
6
6
h/w program
coding
3V3
10K.
RN27 10K.
10k
10k
R184
0
TCKh
R71
RSTCNF hb
TCKs
Pull-Down
5
BREVN0
BREVN1
BREVN2
BCONF0
BCONF1
R9
R10
R11
R7
R8
0
0
0
0
0
Board REV
(*)
(*)
(*)
(*)
(*)
Board CNFG
4
HEE1
32to64ENb
SWOPT0
SWOPT2
SWOPT1
BREVN0
BREVN1
BREVN2
BCONF0
BCONF1
RN31
RN38
STBU FENb
IRQ1 sb
EE0s
UPMWAITsb
IRQ3 sb
NMI sb
DBBsb
IRQ2 sb
IRQ5 sb
RN12
R N8
IRQ2 _2sb
IRQ5 _2sb
IRQ3 _2sb
TAsb
IRQ1 _2sb
IRQ4 _2sb
IRQ 6_2sb
IRQ8 _2sb
4
1
2
3
4
6
7
8
9
2
1
9
4
3
7
6
8
1
2
3
4
6
7
8
9
1
2
3
4
6
7
8
9
10K.
10K.
10K.
10K.
3V3
3V3
3V3
3V3
3
MODCK3h
MODCK2h
MODCK1h
MODCK6h
MODCK5h
MODCK4h
FCFG_ENb
MODC K2s
MODC K1s
DS I2SYS
AR TRYsb
GA3
GA1
GA0
GA2
RN 30
R N5
DREQ1 sb
DREQ2 sb
DREQ3 sb
DREQ4 sb
RN 18
R N6
IRQ 9_2sb
IRQ 11_2sb
IRQ 12_2sb
IRQ 10_2sb
IRQ7 _2sb
IRQ 14_2sb
IRQ 15_2sb
IRQ 13_2sb
3
1
2
3
4
6
7
8
9
1
2
3
4
6
7
8
9
1
2
3
4
6
7
8
9
1
2
3
4
6
7
8
9
10K.
10K.
10K.
10K.
2
RN35
1
2
3
4
6
7
8
9
1
2
3
4
6
7
8
9
1
2
3
4
6
7
8
9
1
2
3
4
6
7
8
9
10K.
10K.
10K.
10K.
3V3
3V3
Abort-h
DBGs_ ENb
DBG h_ENb
Soft Rst-s
Abort-s
SYS64
EE0h
EE1h
NMIhb
HRST1b
So ftRst-h
HardRst -s
HardR st-h
HRST3b
HRST2b
IRQ1hb
IRQ2hb
IRQ3hb
IRQ4hb
IRQ6hb
IRQ5hb
DBBhb
IRQ7hb
RN39
RN34
3V3
3V3
3V3
3V3
RN55
ABBhb
ARTRYhb
AAC Khb
TShb
2
3V3
3V3
HSGA0
HSGA1
HSGA2
HSGA3
EXTMST
RN 10
RN 37
ChainSel2
ChainSel1
TAhb
SY SENb
Motorola Semiconductor Israel Ltd.
MSC8102ADS
1
2
3
4
6
7
8
9
1
2
3
4
6
7
8
9
1
10K.
10K.
1
Sheet
Pull-Ups/Downs
Tuesday, August 13, 2002
Document Number
Metrowerks Israel
1 Shen kar street
Herzelia 46120 Isra el
Title
Size
B
Date:
3V3
3V3
13
of
15
P ILOT
R ev
D
C
B
A
127
MSC8102ADSUM/D Ver. 1.2
User’s Manual
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
Figure 5-18 Schematics. Page 13
Support Info
C105
VC CSYNs
0.1 uF
GNDPL Ls
5
0.01uF
POWER
MSC8102
1V5s
3
C123 0. 01uF
0. 01uF
0. 01uF
C98
C119 0. 01uF
0. 01uF
0. 01uF
C96
C99
C94
0. 01uF
0. 01uF
0. 01uF
C93
C92
0. 01uF
C91
C97
C103 0. 01uF
0. 01uF
C104 0. 01uF
C90
C112 0. 01uF
C125 0. 01uF
C95
0. 01uF
C102 0. 01uF
N13
N12
N10
N8
N6
N4
N3
K13
K2
H13
G4
G2
F13
F4
E2
D13
D3
C2
B10
B6
B4
N7
G5
G13
B8
N14
B1
J3
H4
K4
H6
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
2
U30B
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VDDI
VDDI
VDDI
VDDI
PM5384-NI
VSSI
VSSI
VSSI
VSSI
VSSQ
VSSQ
QAVS
AVD1
VDDQ
VDDQ
QAVD
VSST
AVD0
AVS1
AVS0
ATP
Thermal Island
F12
M12
M10
M8
M6
M4
K12
K3
H12
G3
G1
F3
E3
E1
D12
C10
C6
C4
C1
F5
M7
G12
C8
H5
P14
A1
J4
K5
3V3
C54
+
3V3
C293
0. 1uF
10uF
R204 2.7
R203 2.7
C285
2V5
10uF
Motorola Semiconductor Israel Ltd.
Metrowerks Israel
1 Shen kar street
Herzelia 46120 Isra el
MSC8102ADS
Tuesday, August 13, 2002
Document Number
Title
Size
B
1
C280
C290
C275
C288
C271
C287
C266
C282
C277
C281
0.1 uF
C261
C274
C273
C289
14
C286
C264
C279
C278
C262
C283
C263
C276
3V3
C55
+
1
Sheet
Parts Powering
Date:
of
0.1uF
C107
B3
B8
B10
B12
B14
B16
B18
B20
B21
AB22
C3
C9
C11
C13
D10
D12
D14
D15
E9
E11
E13
E16
F8
F9
F10
F12
F14
F16
G8
G9
G13
G15
G16
H4
H9
H15
H20
J4
J9
J13
J15
K15
M8
R11
R12
R13
T11
Y6
AA2
3V3Qs
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
2
0. 1uF
0.01uF
0.01uF
C110
0.01uF
C108
4
0.01uF
C100 C120 C126
0.01uF
C124 C111 C109 C101
0.01uF
C121 C122
3V3IOs
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCSYN
GNDSYN
3
15
P ILOT
R ev
D
C
B
A
Figure 5-19 Schematics. Page 14
0. 1uF
0.1uF
U7C
B4
B5
B7
B9
B11
B13
B15
B17
B22
AB2
C2
C8
C10
C12
C14
C15
D9
D11
D13
E8
E10
E12
E14
E15
F7
F11
F13
F15
J6
J14
J20
K11
K12
L10
L14
M10
M14
N10
N14
P10
P13
P14
W6
W19
P12
P11
4
1
2
0.01uF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
C
B
A
5
MSC8102ADSUM/D Ver. 1.2
User’s Manual
128
1
2
NC_TH
NC_TH
NC_TH
NC_TH
NC_TH
NC_TH
NC_TH
NC_TH
F8
G6
G7
G8
H7
H8
H9
J7
0.01uF
M4
M20
W7
0.01uF
VDDH
VDDH
VDDH
0.01uF
D20
H21
R3
V3
Y4
AA9
AA12
AA14
L19
L15
P20
U20
Y20
W12
W17
Y10
Y13
M17
W15
M18
L5
M9
N7
L6
D18
D6
W8
M15
Y16
0.01uF
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
D5
D21
E18
G20
K13
K19
L9
L16
L17
M5
M6
M7
M19
P21
R4
T20
V4
V15
W5
W9
W13
W20
Y9
Y12
Y15
Y17
AA8
AA13
AA16
E17
K10
Support Info
D
2
1
1
2
3
U 36
IN
EN
OUT
ADJ
3
1
8
"0"
7
"I"
3
4
5
S W8A
2
DPDT
0mm
D1
3V3
L EDDRVh
R210
150
4
U35B
LE DDRVs
R211
150
2
U35A
1V 5h
MBRD 620CT
4A
F1
Fuse Block 5x2
Set to
1.6V
R 214
3.0k
10k
R 213
R219
150
R P1
WI PER
R212
2
4
C291
1 nF
C292
+ 12V
-1 2V
10uF
C 53
3V3 IOh
3V3
1 nF
4.7k
R 208
C294
0.1uF
C 297
3V3
3V3
0.1uF
R 209
4.7k
1
2
+
U 32
3
4
3V3E xt
+ 3V3
6
4
S W8B
"0"
"I"
+Vout
FEC15- 12S33
5
+Vin
-Vout
DPDT
4
NC
C268
0.1uF
R191
20
R190
20
+ C 51
10uF
GNDPLLh
+ C 52
10uF
C9
3V3IOs
Close to
MSC8101
GNDPLLh
1V5s
+
10uF
10uF
+ C8
C269
0.1uF
3V3Qs
5
0.1uF
C 83
VCCSYNs
0.1uF
C 82
VCCSY N2
0.1uF
C270
VCCSY N1
DC-DC
12V - >3.3V,4A
-Vin
C 56
3V3 Qh
+
47uF
J S3
J S1
J S2
20
R 47
MSC8102
Power Bridge
47uF
+ C 61
G NDPLLs
Close to
MSC8102
3V3
+
C 58
47uF
3V3
1 uF
C296
1
MIC52 09-2.5BS
C2
C 62
0.1uF -500V
C1
0.1uF -500V
U 33
IN
GND
2
4
TAB
OUT
3V3
3V3
D3
LL 4004
D5
LL 4004
D7
3
LL 4004
+ C 59
D6
G NDD
2V5
C295
LL 4004
1V 5h
0.1uF
D4
10uF
LL 4004
1V5s
Host P ower-Up protection circuit
G ND
GNDPLLh
3
D2
J G1
B H1
1 2
J G2
Slave Power-Up protection circuit
LL 4004
G NDPLLs
2
3
1V 5h
2
IN
U 57
OUT
1.0V±2%
VSS
S-8081 0ANNP
4
3,13
8,1 1,13
6, 10
6,7
6,10
1 2
DBBhb
D BBsb
CO DEC_ENb
RS232EN _1b
RS232EN _2b
L EDDRVh
LE DDRVs
6 L EDENb
B H3
Mounting Holes
BH2
CHASIS GROUND
J G3
GND Bridge
1 2
1
B H4
1
4
1 2
BH5
1k
R ED
2
3
PRESET
R122
J G4
SW9
R215
10k
R216
1
2
5
4
3
74LCX541
10k
G1
G2
D5
D3
D8
D4
D2
D6
D7
D1
U 53
1V5s
6
4
9
5
3
7
8
2
1
19
J G5
2
U 34
MON
WDI
14
16
11
15
17
13
12
18
MR
O5
O3
O8
O4
O2
O6
O7
O1
3V3
6
VCC
RST
1
GND
MAX682 8S
2
3V3
0.1uF
C 211
6
6
6
6
6
EE1sLD
SIGS1LD
SIGS0LD
S IGH1LD
S IGH0LD
J P7
10k
R218
D8
3V3
1 0k
R 217
L D4
L D3
L ED GREEN
L ED GREEN
L D2
LED YELLOW
L D5
LED YELLOW
L D8
LED YELLOW
L D7
L ED GREEN
L D6
LED ORANGE
L D10
L ED GREEN
L D9
LED ORANGE
L D1
L D15
L ED GREEN
L ED GREEN
L D16
L ED GREEN
L D12
L D11
L ED GREEN
L ED GREEN
Met rowerks Israel
1 Shenk ar street
Her zelia 46120 Israel
Document Nu mber
Tit le
Tuesday, Augus
1
PR STb
R207
3,5,6 ,11
RUN-h
RUN-s
CODEC
RS232-h
RS232-s
SIG0-h
SIG1-h
SIG0-s
SIG1-s
DBGs
1.5V-h
1.5V-s
3.3V
5VExt
5VExt
3V3
PRS Tsb 5,6,8 ,11,12
R115
R116
150
150
R114
150
R117
150
R125
150
R123
R124
150
150
R130
150
R131
150
R 63
150
150
R206
R138
150
R139
150
330
t 13, 2002
1
Sh eet
15
POWER & LEDs, Unused parts
Date:
Size
C
MSC8102ADS
Motorola Se miconductor Israel Ltd.
D9
4148D
414 8D
1
2
P23
RAPC722
C 57
4
MIC 39102BM
OUT
5
A
1K
B
390
1
2
of
15
PIL OT
R ev
D
C
B
A
129
MSC8102ADSUM/D Ver. 1.2
User’s Manual
MSC8101 Pow er
3V3
+
47uF
EN
IN
U 37
MSC8102 Pow er
3V3
2
1
MIC291 52BU
6
TAB
ADJ
3
GND
1.35V-1.7V
Adjust
Available
C 60
0.1uF -500V
CHASIS GROUND
0.1uF -500V
1
2
1
1
8
1
2
1
2
4
1
2
C
B
A
5
1
2
GND
GND
GND
GND
8
7
6
5
3
MMDF4N0 1HD
MMDF4N01 HD
7
5
6
3
DC 9-18V@1. 8A
Figure 5-20 Schematics. Page 15
Support Info
130
MSC8102ADSUM/D Ver. 1.2
User’s Manual
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MSC8102ADSUM/D