Download 1775-6.4.1, PLC-3 Family Programmable Controller, Programming

I–2
Index
checksum
housekeeping, 13-15
ladder-program status words, 14-19
clear fault command, 13-13
clock tolerance, 5-4
contexts, 13-16
control word for
bit-shift instructions, 9-5
block-transfer instructions, 15-4
counters, 5-13 , 14-5
diagnostic instructions, 12-2
FIFO instructions, 9-8
file-data-comparison instructions, 8-14
file-data-transfer instructions, 8-5
files, 7-14
message instruction, 16-2
pointer operation, 11-8
timers, 5-2 , 14-5
conversion
of data for data-manipulation instructions, 6-4 , 8-5
status bits, 14-15
tables, B-7
two’s complement for negative numbers, B-6
converted procedures, 2-5 , 2-7 , 14-2 , 14-10
counter
cascading, 5-21
down (CTD) instruction, 5-18
execution times, A-4
extended address, 14-5
files, 7-11
in pointers, 11-7
operation for
bit-shift instructions, 9-5
counter instructions, 5-12–5-15
diagnostic instructions, 12-2
FIFO instructions, 9-8
files, 7-14 , 8-5
indexed-logic instructions, 10-2
none mode, 7-22
range, 3-3
reset (RES) instruction, 5-21
table, 3-6
up (CTU) instruction, 5-16
CTD counter-down instruction, 5-18
execution times, A-4
CTU counter-up instruction, 5-16
execution times, A-4
D
data
comparison, 6-8 , 8-14
highway messages, 16-8 , 16-9
table
defined, 2-3 , 2-6 , 3-1–3-8
extended addressing, 14-3 , 14-4
map, 3-2 , 6-2 , 8-3
type, 3-3 , 6-3 , 8-4
DDT diagnostic-detect instruction, 12-5
I–2
decimal table, 3-7
delimiter
file (F), 7-3 , 7-8 , 8-2
word (W), 7-6 , 7-8 , 8-2
destination address (R), 6-4 , 8-5
diagnostic
block-transfer program, 15-14
considerations for writing the progarm, 17-2 , 17-3
detect (DDT) instruction, 12-5
done bit, 12-2
enable bit, 12-3
error bit, 12-2
found bit, 12-3
instructions, 12-1–12-3
routine (change-of-state), 12-6–12-25
DIV divide instruction, 6-17
execution times, A-7
DVF file-divide instruction, 8-34
E
END instruction, 13-9
EQU equal-to instruction, 6-8
execution times, A-5
examine
indexed bit off (XIF) instruction, 10-5
indexed bit on (XIN) instruction, 10-4
off (XIC) instruction, 4-11
on (XIC) instruction, 4-11
execution times for instruction set, A-1
extended addressing
defined, 14-1–14-12
in message instruction, 16-4
in move-status instruction, 6-7 , 14-1–14-12
F
fault routine
label, 13-5
operation, 13-10–13-13
specifying in extended addressing, 14-6
FBC file-bit-compare instruction, 12-3
FFL FIFO-load instruction, 9-10
FFU, FIFO-unload instructions, 9-11
FIFO operation, 9-8–9-10
file
add (ADF) instruction, 8-28
addressing, 7-3–7-13
AND (ANF) instruction, 8-41
execution times, A-9
arithmetic instructions, 8-2 , 8-27
bit compare (FBC) instruction, 12-3
block-transfer control, 15-4
counter operation, 7-14
creating, 7-3
data-comparison instructions, 8-2 , 8-14
data-transfer instructions, 8-2 , 8-5
defined, 7-1
diagnostic operation with a, 12-1