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PNX17xx Series NXP Semiconductors Volume 1 of 1 Chapter 1: Integrated Circuit Data 3. See timing measurement conditions Figure 22. CLOCK TCLK-DV valid DATA CLOCK TSU-CLK TH-CLK valid DATA TVALID Figure 22: Audio Output I/O Timing 7.13 JTAG Interface Table 44: JTAG Timing Symbol Parameter FBSCAN Min Max Units Notes Boundary scan frequency 15 MHz FJTAG JTAG frequency 20 MHz TCLK-DV Falling edge of the JTAG_TCK to JTAG_TDO 0 8 ns Figure 23 TSU-CLK Input setup time 8 ns Figure 23 TH-CLK Input hold time 3 ns Figure 23 JTAG_TCK TSU-TCK TH-TCK JTAG_TDI JTAG_TMS valid JTAG_TCK TCLK-DV JTAG_TDO valid Figure 23: JTAG I/O Timing PNX17XX_SER_1.11 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 1.11 — 05 February 2007 1-45
