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Download ADSP-219x/2191 DSP Hardware Reference
Transcript
Setting Peripheral DMA Modes • The SPI DMA Configuration (SPIxD_CFG) registers have bits that differ from the other channel’s configuration registers: DMA SPI Receive Busy (Overflow Error) Status. SPIxD_CFG bit 9 (RBSY) This bit—only on an SPI port DMA channel with TRAN=1—indicates that the SPI port buffer has overflowed (if set, =1) or has not overflowed (if cleared, =0). (read-only) DMA SPI Transmit (Underflow) Error Status. SPIxD_CFG bit 10 (TXE) This bit—only on an SPI port DMA channel with TRAN=0—indicates that the SPI port buffer has underflowed (if set, =1) or has not underflowed (if cleared, =0). (read-only) DMA SPI Mode Fault (Multi-master Error) Status. SPIxD_CFG bit 11 (MODF) This bit indicates that another SPI master has aborted (if set, =1) or has not aborted (if cleared, =0) the current DMA transfer. (read-only) For information on these channels other settings, see Table 6-1 on page 6-17, Table 6-2 on page 6-18, and the xxxx_CFG register discussion on page 6-19. For information on using these DMA channels, see “Using SPI Port DMA” on page 6-33. 6-24 ADSP-219x/2191 DSP Hardware Reference
