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Download ADSP-2137x SHARC ® Processor Hardware
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I/O Processor Chain pointer registers. Shown in Table 2-5, chain pointer registers hold the starting address of the TCB (parameter register values) for the next DMA operation on the corresponding channel. These registers also control whether the I/O processor generates an interrupt when the current DMA process ends. Table 2-5. Chain Pointer Registers Register Name Width (Bits) Description CPSP0-7A 29 SPORTA CPSP0-7B 29 SPORTB CPSPI 20 SPI CPSPIB 20 SPIB CPUART0RX 20 UART0 Receiver CPUART1RX 20 UART1 Receiver CPUART0TX 20 UART0 Transmitter CPUART1TX 20 UART1 Transmitter CPEP0-1 21 External Port Extended DMA Parameter Registers This section describes the enhanced parameter registers used for the external port. Base registers. Shown in Table 2-6, base registers indicate the start address of the circular buffer to be transferred to/from memory on the corresponding DMA channel. ADSP-2137x SHARC Processor Hardware Reference 2-7
