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library ieee;
use ieee.std_logic_1164.all;
-- low-level design
-- your VHDL entity
entity cnt4 is
port(cout: out bit;
output: out bit_vector (3 downto 0);
input: in bit_vector (3 downto 0);
ce, load, clk, rst: in bit);
end cnt4;
-- your VHDL architecture
architecture behave of cnt 4 is
begin
--- your code
-end behave;
--- New top level entity created to specifically place I/Os for
Xilinx
-- This entity typically would be in another file, so your
original
-- design stays untouched and technology independent.
-library ieee;
use ieee.std_logic_1164.all;
library xc4000;
Page 4.589.7
use xc4000.components.all;