Download PC104-30F/G User`s Manual

Index
PC104-30F and PC104-30G Series User’s Manual
Introduction.................................................................................................6-1
Loading the Channel List/Block Counter .....................................................6-6
Obtaining a Series of A/D Conversions by Polled I/O..................................6-7
Obtaining a Single A/D Reading..................................................................6-5
Setting Channel Gain...................................................................................6-4
Setting the Sample Rate...............................................................................6-5
Single Channel DMA ..................................................................................6-8
Writing to the D/A Converters.....................................................................6-4
Recommended Analogue Input Schemes .........................................................4-7
Register Configuration
DMA/IRQ Config Register...............................................................5-25, 5-27
Register Structure
A/D Clock Divider Register ......................................................................5-13
A/D Clock Prescaler Register ....................................................................5-12
A/D Control/Channel Register.....................................................................5-7
A/D Data Low Byte.....................................................................................5-4
A/D Data/Status Register ............................................................................5-5
A/D Mode Register .....................................................................................5-8
Block Counter .............................................................................................5-4
DAC0 Register (Low Byte) .......................................................................5-23
DAC0 Register High Byte .........................................................................5-24
DAC1 Register (Low Byte) .......................................................................5-24
DAC1 Register High Byte .........................................................................5-25
DAC2 Register (Low Byte) .......................................................................5-31
DAC2 Register High Byte .........................................................................5-31
DAC3 Register (Low Byte) .......................................................................5-31
DAC3 Register High Byte .........................................................................5-32
Digital I/O Control ....................................................................................5-21
Digital I/O Port 0.......................................................................................5-19
Digital I/O Port 1.......................................................................................5-19
Digital I/O Port 2.......................................................................................5-20
Gain Memory 0 Register ...........................................................................5-35
Gain Memory 1 Register ...........................................................................5-36
Gain Memory 2 Register ...........................................................................5-37
Gain Memory 3 Register ...........................................................................5-38
Gain Read Back and Board Type Register.................................................5-32
Timer Control Register ..............................................................................5-15
User Counter Register ...............................................................................5-14
Selection of DMA Levels ..............................................................................3-14
Signal Definitions
+5V.............................................................................................................4-5
Analogue Ground ........................................................................................4-2
CH0 - CH15 ................................................................................................4-2
DAC0 Output ..............................................................................................4-3
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