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ARC Four Execution Unit (AFEU)
the key size register indicates 2 key 3DES is to be performed (key size = 16 bytes). To
operate in 168-bit Triple DES, key register 1 must be written first, followed by the write of
key register 2, the key register 3.
Reading any of these memory locations will generate an address error interrupt.
Freescale Semiconductor, Inc...
4.2.12 DEU FIFOs
DEU uses an input FIFO/output FIFO pair to hold data before and after the encryption
process. These FIFOs are multiply addressable, but those multiple addresses point only to
the appropriate end of the appropriate FIFO. A write to anywhere in the DEU FIFO address
space causes the 64-bit-word to be pushed onto the DEU input FIFO, and a read from
anywhere in the DEU FIFO Address space causes a 64-bit-word to be popped off of the
DEU output FIFO. Overflows and underflows caused by reading or writing the DEU FIFOs
are reflected in the DEU interrupt status register.
4.3
ARC Four Execution Unit (AFEU)
This section contains details about the ARC Four Execution Unit (AFEU), including
detailed register map, modes of operation, status and control registers, S-box memory, and
FIFOs.
4.3.1
AFEU Register Map
The registers used in the AFEU are documented primarily for debug and target mode
operations. If the MPC185 requires the use of the AFEU when acting as an initiator,
accessing these registers directly is unnecessary. The device drivers and the on-chip
controller will abstract register level access from the user. The AFEU contains the following
registers:
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AFEU Mode Register
Key Size Register
Data Size Register
Reset Control Register
Status Register
Interrupt Status Register
Interrupt Control Register
End Of Message Register
Context Memory
Context Pointer Register
Key Registers
FIFO
MPC185 Security Co-Processor User’s Manual
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