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Download ADSP-2189M DSP Microcomputer
Transcript
ADSP-2189M Parameter Min Bus Request–Bus Grant Timing Requirements: tBH BR Hold after CLKOUT High1 BR Setup before CLKOUT Low1 tBS 0.25tCK + 2 0.25tCK + 10 Switching Characteristics: tSD tSDB tSE tSEC tSDBH tSEH 0 0 0.25tCK – 3 0 0 CLKOUT High to xMS, RD, WR Disable xMS, RD, WR Disable to BG Low BG High to xMS, RD, WR Enable xMS, RD, WR Enable to CLKOUT High xMS, RD, WR Disable to BGH Low2 BGH High to xMS, RD, WR Enable2 Max Unit ns ns 0.25tCK + 8 ns ns ns ns ns ns NOTES xMS = PMS, DMS, CMS, IOMS, BMS 1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. tBH CLKOUT BR tBS CLKOUT PMS, DMS BMS, RD WR BG BGH tSD tSEC tSDB tSE tSDBH tSEH Figure 24. Bus Request–Bus Grant REV. A –21–
