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MPC7450 Execution Latencies
Table 48. Store Unit (LSU) Instruction Latencies (continued)
MPC750
Mnemonic
MPC7400
MPC7450
Class
Unit
Cycles
Unit
Cycles
Unit
Cycles
sthux
GPR
LSU
2:1
LSU
2:1 {s}
LSU
3:1 {s}
sthx
GPR
LSU
2:1
LSU
2:1 {s}
LSU
3:1 {s}
stmw
N/A
LSU
2+n {e}
LSU
2+n {e}
LSU
3 + n{s}
stswi
GPR
LSU
2+n {e}
LSU
2+n {e}
LSU
3+ n{s}
stswx
GPR
LSU
2+n {e}
LSU
2+n {e}
LSU
3 + n{s}
stvebx
Vector
N/A
N/A
LSU
2:1
LSU
3:1{s}
stvehx
Vector
N/A
N/A
LSU
2:1
LSU
3:1{s}
stvewx
Vector
N/A
N/A
LSU
2:1
LSU
3:1{s}
stvx
Vector
N/A
N/A
LSU
2:1
LSU
3:1{s}
stvxl
Vector
N/A
N/A
LSU
2:1 {s}
LSU
3:1{s}
stw
GPR
LSU
2:1
LSU
2:1 {s}
LSU
3:1{s}
stwbrx
GPR
LSU
2:1
LSU
2:1 {s}
LSU
3:1{s}
stwcx.
GPR
LSU
8:8 {e}
LSU
5:5 {s}
LSU
3:1{s}
stwu
GPR
LSU
2:1
LSU
2:1 {s}
LSU
3:1{s}
stwux
GPR
LSU
2:1
LSU
2:1 {s}
LSU
3:1{s}
stwx
GPR
LSU
2:1
LSU
2:1 {s}
LSU
3:1{s}
tlbie
N/A
LSU
3:4
LSU
2:3*b {s}
LSU
3:1{s}
tlbld
N/A
N/A
N/A
N/A
N/A
LSU
3{e}
tlbli
N/A
N/A
N/A
N/A
N/A
LSU
3{e}
1
For cache operations, the first number indicates the latency for finishing a single
instruction, and the second number indicates the throughput for a large number of
back-to-back cache operations. The throughput cycle may be larger than the initial
latency because more cycles may be needed for the data to reach the cache. If the
cache remains busy, subsequent cache operations cannot execute.
2
Floating-point stores may take as many as 24 additional cycles if the value being
stored is a denormalized number.
Table 49 lists vector simple integer instruction latencies. This simple integer unit is called the VSIU in the
MPC7400 and the VIU1 in the MPC7450.
Table 49. AltiVec Operations—Vector Simple Integer Unit
MPC7400
MPC7450
Mnemonic
Unit
Cycles
Unit
Cycles
vaddcuw
VALU-VSIU
1
VIU1
1
vaddsbs
VALU-VSIU
1
VIU1
1
MPC7450 RISC Microprocessor Family Software Optimization Guide, Rev. 2
Freescale Semiconductor
69