Download MPC7450 RISC Microprocessor Family Software Optimization Guide

Overview of Target Microprocessors
Table 4. MPC7450 Pipeline Stages
Pipeline Stage
Abbreviation
Comment
Fetch1
F1
First stage of reading from instruction cache
Fetch2
F2
Second stage of reading from instruction cache
Branch execute
BE
Execute branch and redirect fetch if needed
Dispatch
D
Decode, dispatch to IQs, assigned to rename register
Issue
I
Issue to execution units, register file read
Execute
E, E0, E1, ...
Instruction execution
Completion
C
Instruction completion
Write-back
WB
Architectural update
The MPC7450 pipeline is longer than the MPC750/MPC7400 pipeline, particularly in the primary load
execution part of the pipeline (3 cycles versis 2 cycles). Faster processor performance often requires
designs to operate at higher clock speeds. Clock speed is inversely related to the work performance of the
processor. Therefore, higher clock speeds imply less work to be performed per cycle, which necessitates
longer pipelines. Also, increased density of the transistors on the chip has enabled the addition of
sophisticated branch-prediction hardware, additional processor resources, and out-of-order execution
capability. This industry trend should continue for at least one more microprocessor generation. The longer
pipelines yield a processor more sensitive to code selection and ordering. Because hardware can add
additional resources and out-of-order processing ability to reduce this sensitivity, the hardware and the
software must work together to achieve optimal performance.
3
Overview of Target Microprocessors
This section provides a high-level overview of the three target microprocessors, with first-order details that
are useful in developing a compiler model of the microprocessor.
3.1
MPC750 Microprocessor
Figure 3 shows a functional block diagram of the MPC750.
MPC7450 RISC Microprocessor Family Software Optimization Guide, Rev. 2
Freescale Semiconductor
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