1
Download "user manual"
Transcript
Electrical Characteristics Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 12. S0 S1 S2 S3 S4 S5 S0 S1 CLKOUT B6a B7a CSn B8 B9 A[23:0] TSIZ[1:0] B8 B9 TS B8 B9 TIP B6c OE B7 R/W (H) B6b B7 BS[3:0] B5 B4 D[31:0] B2a TA B1a TEA (H) Figure 9. SRAM Read Bus Cycle Terminated by TA MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 26 Freescale Semiconductor
