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Electrical Characteristics TCLK VIL VIH J5 Data Inputs J6 Input Data Valid J7 Data Outputs Output Data Valid J8 Data Outputs J7 Data Outputs Output Data Valid Figure 22. Boundary Scan (JTAG) Timing TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 23. Test Access Port Timing TCLK J14 TRST J13 Figure 24. TRST Timing MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 37
