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5.1
Watchdog Timer Overview
The primary function of the watchdog timer is to monitor the cPCI-6830’s
operation and take corrective action if the software fails to function as
programmed. The major features of the watchdog timer are:
• Two-stage
• Enabled and disabled through software control
• Armed and strobed through software control
Address/Data
Port 3F0h
Control
and status
Register
Watchdog Circuit
Slow Clock
Reset
NMI
CPU Init
Counter
Figure 5: Watchdog Timer Architecture
The cPCI-6830’s custom watchdog timer circuit is implemented in a
programmable logic device. The watchdog timer contains a "Control and
Status Register". The register allows the BIOS or user applications to
determine if a watchdog time out was the source of a particular reset.
The watchdog timer drives the First and Second Stages as follows:
The watchdog times out (First Stage) after a selected timeout interval.
NMI or INIT (software selectable) is driven high.
A hard reset occurs (Second Stage).
The timeout period is 1 – 255 seconds or 1 – 255 minutes. The watchdog is
normally strobed by reading the Watchdog Register (3F0h). This clears the
counter. Writes to this register also clear the counter.
50 • Utilities